CY8C52_11 Datasheet, PDF (82/94 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C52 Family Datasheet
11.5.2 Voltage Monitors
Table 11-51. Voltage Monitors DC Specifications
Parameter
Description
LVI
Trip voltage
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
Table 11-52. Voltage Monitors AC Specifications
Parameter
Description
Response time
11.5.3 Interrupt Controller
Table 11-53. Interrupt Controller AC Specifications
Parameter
Description
Delay from interrupt signal input to ISR
code execution from main line code
Delay from interrupt signal input to ISR
code execution from ISR code
(tail-chaining)
Conditions
Conditions
Conditions
Min
Typ
Max
Units
1.68
1.73
1.77
V
1.89
1.95
2.01
V
2.14
2.20
2.27
V
2.38
2.45
2.53
V
2.62
2.71
2.79
V
2.87
2.95
3.04
V
3.11
3.21
3.31
V
3.35
3.46
3.56
V
3.59
3.70
3.81
V
3.84
3.95
4.07
V
4.08
4.20
4.33
V
4.32
4.45
4.59
V
4.56
4.70
4.84
V
4.83
4.98
5.13
V
5.05
5.21
5.37
V
5.30
5.47
5.63
V
5.57
5.75
5.92
V
Min
Typ
–
–
Max
Units
1
µs
Min Typ Max Units
–
–
12 Tcy CPU
–
–
6 Tcy CPU
Document Number: 001-66236 Rev. **
Page 82 of 94
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