CY8C52_11 Datasheet, PDF (36/94 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C52 Family Datasheet
Input from
Programmable
Routing
Input
Muxes
6
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
Figure 7-8. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
F1
FIFOs
F0
A0
A1
D1
D0
D1
Data Registers
D0
To/From
Previous
A1
Datapath
Accumulators
A0
Output
Muxes
6
Output to
Programmable
Routing
Chaining
To/From
Next
Datapath
ALU
Shift
Mask
7.2.2.6 Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Table 7-1. Working Datapath Registers
Name
Function
A0 and A1 Accumulators
D0 and D1 Data Registers
F0 and F1 FIFOs
Description
These are sources and sinks for
the ALU and also sources for the
compares.
These are sources for the ALU
and sources for the compares.
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumu-
lators or ALU. Each FIFO is four
bytes deep.
7.2.2.7 Dynamic Datapath Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the 8-word
× 16-bit configuration RAM, which stores eight unique 16-bit
wide configurations. The address input to this RAM controls the
sequence, and can be routed from any block connected to the
UDB routing matrix, most typically PLD logic, I/O pins, or from
the outputs of this or other datapath blocks.
ALU
The ALU performs eight general purpose functions. They are:
„ Increment
„ Decrement
„ Add
„ Subtract
„ Logical AND
„ Logical OR
„ Logical XOR
„ Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
Independent of the ALU operation, these functions are available:
„ Shift left
„ Shift right
„ Nibble swap
„ Bitwise OR mask
Document Number: 001-66236 Rev. **
Page 36 of 94
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