CYRF8935_13 Datasheet, PDF (8/40 Pages) Cypress Semiconductor – WirelessUSB™-NL 2.4 GHz Low Power Radio

CYRF8935
Receive Timing
Figure 6 shows the Rx timing diagram. The receive process
begins when the MCU writes register 7[7] = 1. At this time, the
CYRF8935 framer turns on the receiver and waits while
attempting to detect a valid syncword. The receive frequency is
specified within register 7. The two register 7 fields of interest,
RX_EN and RF_PLL_CH_NO, may be sent to CYRF8935 during
the same SPI transaction. If sent in separate SPI transactions,
send the RF_PLL_CH_NO first, followed by RX_EN.
If a valid syncword is found, the CYRF8935 framer processes the
packet automatically. When the received packet processing is
complete, the CYRF8935 framer sets the state to IDLE.
If the received packet length is longer than 63 bytes, the FIFO
flag goes active, which means the MCU must read out data from
the FIFO.
A valid syncword might not always be found, either due to a weak
signal, multi-path cancellation, or devices being out of range. To
accommodate such a condition and to prevent lockup, the
application or the MCU must incorporate a 'receive timeout' timer
to clear RX_EN and return to the IDLE state.
Figure 6. Rx Timing Diagram when Register 41[13] = 1 (Framer Handles Packet Length)
PKT and FIFO Flags are Active High
Write Reg. 7
SPI_SS
Internal Rx_on
2 µs
Receive On Delay
Received Data
Rx Packet
PKT = 1 when Rx packet has been
PKT
received by Framer.
FIFO
FIFO = 1 when FIFO is full.
Document Number: 001-61351 Rev. *J
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