CYRF8935_13 Datasheet, PDF (11/40 Pages) Cypress Semiconductor – WirelessUSB™-NL 2.4 GHz Low Power Radio

CYRF8935
FW_TERM_TX= 0 (Receive)
When register 41[13] = 0, packet reception starts when MCU or
application writes register 7[7] RX_EN = 1. At this time, the
framer automatically turns on the receiver to the frequency and
channel specified in register 7. After waiting for the internal
synthesizer and receiver delays, the framer circuitry of the
CYRF8935 begins searching the incoming signal for a syncword.
When the syncword is detected, the framer sets the PKT flag
active, and then starts to fill the FIFO with receive data bytes. The
PKT flag remains active until the MCU or application reads out
the first byte of data from the FIFO register. After the MCU or
application reads the first byte of receive data, the PKT flag goes
inactive until the next Tx/Rx period.
With register 41[13:12] = '00b or '01b, the CYRF8935 framer
always needs the MCU or application to write register 7[7] to 0
to stop the Rx state.
The Rx timing diagram is shown in Figure 9.
Write
Reg. 7
SPI_SS
Figure 9. RX Timing Diagram when Register 41[13:12] = '00b or '01b
PKT_flag and FIFO_flag are Active High
Write
Reg. 7
Internal Rx On
2 µs
Internal Rx Data
Internal Rx On Delay
2 µs
Packet Rx Data
PKT
PKT = 1 when syncword received.
PKT = 0 when MCU/application reads first byte from FIFO register.
FIFO
FIFO = 1 when FIFO is full.
Document Number: 001-61351 Rev. *J
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