CYRF8935_13 Datasheet, PDF (14/40 Pages) Cypress Semiconductor – WirelessUSB™-NL 2.4 GHz Low Power Radio

CYRF8935
Figure 10. Simplified Schematic of Crystal Oscillator
CRYSTAL
C2
C1
Rs
Rf
Xtal. Osc.
Gain Block
Clock
Logic
CYRF8935
BRCLK
(bare die only)
Connect to
Frequency Counter
to verify correct
crystal osc. frequency.
Figure 11. Reset Pull-up Circuit
Vin
R5
10k
RST_n
13 _{SPI_SS}
14 _PKT
15 _CLK
16 _MOSI
17 _MISO
18 _{RST_n}
25
GND
U1
Test2 ⁶
VDD3 ⁵
ANT ⁴
ANTb ³
VDD2 ²
VDD1 ¹
Note When crystal oscillator is constructed as shown in Typical
Application on page 12, Table 5 on page 13, and Figure 10, the
oscillation frequency should be stable within 3 mS (max) after
startup.
Minimum Pin Count
When a low-cost MCU drives the CYRF8935, the MCU pin count
must be minimized.
■ FIFO pin: Only needed when the Tx or Rx packet length is
greater than around 63 bytes, up to infinity. For short packets
(< 63 bytes), FIFO is not needed.
■ PKT pin: Gives a hardware indication of a packet received. If
you are willing to poll register 48 for this information, then this
pin is not needed.
■ SPI lines: All four lines are needed.
Reset Pull-up
For proper power-up initialization, the RST_n pin must have a
pull-up to VIN, as shown in Figure 11. The exact value of the 10-k
pull-up resistor is not critical. The pull-up resistor ensures proper
operation of the CYRF8935 internal-level shifter circuitry while
power is applied. Subsequently, the RST_npulse resets the
internal registers to their default state.
CYRF8935
Vin
Transmit Power Control
Table 6 lists recommended settings for register 9 for short-range
applications, where reduced transmit RF power is a desirable
trade off for lower current.:
Table 6. Transmit Power Control
Power Setting
Description
PA0 - Highest power
PA2 - High power
PA4 - High power
PA8 - Low power
PA12 - Lower power
Typical
Transmit
Power
(dBm)
+1
0
–3
–7.5
–11.2
Value of Register 9
Silicon
0x1002
I_[D_6]
Silicon
0x2002
I_[D_6]
0x1820
0x1920
0x1A20
0x1C20
0x1E20
0x7820
0x7920
0x7A20
0x7C20
0x7E20
Reading RSSI
The CYRF8935 contains internal RSSI circuitry that is roughly
linearized to 1 dB for every LSB. Results are read from register
6[15:10], RAW_RSSI. See Register Definitions on page 21 for
details.
The framer must read the RSSI register after the receiver is
enabled and set on frequency using register 7, and after the RF
PLL has settled according to the correct receive frequency.
Note
6. Silicon Id can be read from Register 31.
Document Number: 001-61351 Rev. *J
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