CY7C2163KV18 Datasheet, PDF (8/30 Pages) Cypress Semiconductor – 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

CY7C2163KV18, CY7C2165KV18
Application Example
Figure 2 shows two QDR II+ used in an application.
Figure 2. Application Example
Vt
R
DATA IN
DATA OUT
Address
BUS MASTER ^RPS
(CPU or ASIC) ^WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
Source K
Source K
R
ODT
ZQ ^{RQ = 250 ohms}
SRAM #1 ^ODT
CQ/CQ
D
Q
D
A RPS WPS BWS K K
A
RQ = 250 ohms
ZQ
SRAM #2
ODT
CQ/CQ
Q
RPS WPS BWS K ^K
R
Vt
Vt
R
R = 50ohms, Vt = VDDQ/2
Document Number: 001-58921 Rev. *F
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