CY7C2163KV18 Datasheet, PDF (28/30 Pages) Cypress Semiconductor – 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Acronyms
Acronym
Description
DDR
double data rate
EIA
electronic industries alliance
FBGA
fine-pitch ball grid array
HSTL
high-speed transceiver logic
I/O
input/output
JEDEC joint electron devices engineering council
JTAG
joint test action group
LMBU
logical multiple bit upset
LSB
least significant bit
LSBU
logical single bit upset
MSB
most significant bit
ODT
on-die termination
PLL
phase locked loop
QDR
quad data rate
SEL
single event latch-up
SRAM
static random access memory
TAP
test access port
TCK
test clock
TDI
test data-in
TDO
test data-out
TMS
test mode select
CY7C2163KV18, CY7C2165KV18
Document Conventions
Units of Measure
Symbol
°C
k
MHz
µA
µs
mA
mm
ms
ns

%
pF
ps
V
W
Unit of Measure
degree Celsius
kilohm
megahertz
microampere
microsecond
milliampere
millimeter
millisecond
nanosecond
ohm
percent
picofarad
picosecond
volt
watt
Document Number: 001-58921 Rev. *F
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