CY14E256L Datasheet, PDF (8/16 Pages) Cypress Semiconductor – 256-Kbit (32K x 8) nvSRAM

PRELIMINARY
AC Switching Characteristics
Parameter
Cypress
Alt.
Parameter Parameter
Description
SRAM Read Cycle
t_ACE
t_RC ^[4]
t_AA ^[5]
t_ACS
t_RC
t_AA
t_DOE
t_OHA ^[5]
t_LZCE ^[6]
t_HZCE ^[6]
t_LZOE ^[6]
t_HZOE ^[6]
t_PU[ ^3]
t_PD ^[3]
t_OE
t_OH
t_LZ
t_HZ
t_OLZ
t_OHZ
t_PA
t_PS
SRAM Write Cycle
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t_WC
t_WC
t_PWE
t_WP
t_SCE
t_CW
t_SD
t_DW
t_HD
t_DH
t_AW
t_AW
t_SA
t_AS
t_HA
t_WR
t_HZWE ^[6,7] t_WZ
t_LZWE ^[6]
t_OW
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Set-Up to End of Write
Data Hold After End of Write
Address Set-Up to End of Write
Address Set-Up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
AutoStore/Power-Up RECALL
Parameter
Description
t_HRECALL ^[8]
t_STORE ^[9]
Power-Up RECALL Duration
STORE Cycle Duration
V_SWITCH
Low Voltage Trigger Level
t_VCCRISE
V_CC Rise Time
Notes:
4. WE must be HIGH during SRAM Read Cycles.
5. Device is continuously selected with CE and OE both Low.
6. Measured ±200mV from steady state output voltage.
7. If WE is Low when CE goes Low, the outputs remain in the high-impedance state.
8. t_HRECALL starts from the time V_CC rises above V_SWITCH.
9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place.
CY14E256L
25ns part
Min. Max.
45ns part
Min. Max. Unit
25
45 ns
25
45
ns
25
45 ns
10
20 ns
5
5
ns
5
5
ns
10
15 ns
0
0
ns
10
15 ns
0
0
ns
25
45 ns
25
45
ns
20
30
ns
20
30
ns
10
15
ns
0
0
ns
20
30
ns
0
0
ns
0
0
ns
10
14 ns
5
5
ns
CY14E256L
Min.
Max.
Unit
550
µs
10
ms
4.0
4.5
V
150
µs
Document #: 001-06968 Rev. *C
Page 8 of 16
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