CY14E256L Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 256-Kbit (32K x 8) nvSRAM

PRELIMINARY
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns and 45 ns Access Times
• “Hands-off” Automatic STORE on Power Down with
external 68µF capacitor
• STORE to QuantumTrap^® Nonvolatile Elements is
initiated by Software, Hardware or Autostore^® on
Power-down
• RECALL to SRAM Initiated by Software or Power-up
• Infinite READ, WRITE and RECALL Cycles
• 15 mA Typical I_CC at 200 ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Commercial Temperature
• SOIC Package
• RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
Infinite read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
Quantum Trap
V_CC
V_CAP
512 X 512
A₅
STORE
POWER
CONTROL
A₆
A₇
A₈
A₉
A ₁₁
A ₁₂
STATIC RAM
ARRAY
512 X 512
RECALL
STORE/
RECALL
CONTROL
HSB
A ₁₃
A ₁₄
SOFTWARE
DETECT
- A₁₃ A₀
DQ ₀
DQ ₁
DQ ₂
DQ ₃
DQ ₄
DQ ₅
DQ ₆
DQ ₇
COLUMN I/O
COLUMN DEC
A₀ A₁ A₂ A₃ A₄ A₁₀
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709
• 408-943-2600
Document #: 001-06968 Rev. *C
Revised November 28, 2006
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