CY14E256L Datasheet, PDF (10/16 Pages) Cypress Semiconductor – 256-Kbit (32K x 8) nvSRAM

Switching Waveforms (continued)
ADDRESS
CE
PRELIMINARY
t_RC
t_LZCE
t_ACE
OE
DQ (DATA OUT)
ICC
t_DOE
tLZOE
t_PU
STANDBY
ACTIVE
CY14E256L
t_PD
t_HZCE
t_HZOE
DATA VALID
ADDRESS
CE
WE
DATA IN
DATA OUT
Figure 7. SRAM Read Cycle #2: CE Controlled ^[4,14]
t_WC
t_SCE
t_HA
t_AW
t_SA
t_PWE
PREVIOUS DATA
t_HZWE
t_SD
DATA VALID
HIGH IMPEDANCE
t_HD
t_LZWE
Figure 8. SRAM Write Cycle #1: WE Controlled ^[14,15]
Note:
15. CE or WE must be > V_IH during address transitions.
Document #: 001-06968 Rev. *C
Page 10 of 16
[+] Feedback