CY8C28243_13 Datasheet, PDF (78/80 Pages) Cypress Semiconductor – PSoC® Programmable System-on-Chip™

CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
1. 10-bit SAR ADC does not meet DNL/INL specification.
■ Problem Definition
The 10-bit hardware SAR ADC does not meet datasheet accuracy specifications for DNL and INL under some conditions.
■ Parameters Affected
INLSAR10: Integral nonlinearity
DNLSAR10: Differential nonlinearity
■ Trigger Condition(S)
The SAR ADC DNL has been measured greater than 2 LSB over temperature in all cases, as compared to the datasheet specification
of 1.5 LSB.
When using the VPWR (Vdd) reference configuration, the SAR ADC DNL has been measured over temperature at 2 LSB for a supply
voltage of 3.3V. With a supply voltage of 5.5V, the DNL has been measured greater than 3.5 LSB.
■ Scope of Impact
Inaccurate converted data.
■ Workaround
❐ Use an alternate ADC implementation (DelSig, ADCINC) available in CY8C28xxx devices.
❐ Avoid CPU operations that change the address and data buses while A-D conversion is running with internal Vpwr (Vdd) as Vref.
❐ Use un-buffered RefHi as ADC Vref. This may have a negative effect on the analog blocks in the analog array due to the noise
introduced on RefHi reference.
■ Fix Status
Silicon fix is planned before full device production starts.
2. Wrong data read from IDAC_CRx and DACx_D registers.
■ Problem Definition
The CPU may read an incorrect value of bits 0, 3, 5, or 7 from the following registers:
❐ IDAC_CR0
❐ IDAC_CR1
❐ DAC0_D
❐ DAC1_D
■ Parameters Affected
FCPU1 and FCPU2 from the device data sheet.
■ Trigger Condition(S)
When CPU Clock is set at its highest frequency setting (24 MHz nominal).
■ Scope of Impact
Incorrect data read from affected registers.
■ Workaround
Temporarily slow down CPU Clock frequency to 12 MHz nominal (or lower) when affected registers are read.
Document Number: 001-48111 Rev. *L
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