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| CY7C4801_02 Datasheet, PDF (7/23 Pages) Cypress Semiconductor – 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs | |||
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Switching Waveforms
Write Cycle Timing
WCLKA (WCLKB)
DA0 âDA8
(DB0âDB8)
WENA1
(WENB1)
WENA2(WENB2)
(if applicable)
FFA (FFB)
RCLKA (RCLKB)
RENA1,RENB2
(RENB1, RENB2)
tCLKH
tCLK
tCLKL
tDS
tENS
tWFF
tSKEW1 [11]
Read Cycle Timing
RCLKA (RCLKB)
RENA1,RENA2
(RENB1,RENB2)
tENS
EFA(EFB)
QA0âQA8
(QB0âQB8)
tOLZ
OEA(OEB)
WCLKA,WCLKB
WENA1(WENB1)
tCLKH
tCLK
tCLKL
tENH
tREF
tA
NO OPERATION
tOE
tSKEW1[12]
CY7C4801/4811/4821
CY7C4831/4841/4851
tDH
tENH
tWFF
NO OPERATION
NO OPERATION
48X1â6
tREF
VALID DATA
tOHZ
WENA2(WENB2)
48X1â7
Notes:
11. tSKEW1 is the minimum time between a rising (RCLKA,RCLKB) edge and a rising (WCLKA,WCLKB) edge to guarantee that (FFA,FFB) will go HIGH during the current clock
cycle. If the time between the rising edge of (RCLKA,RCLKB) and the rising edge of (WCLKA,WCLKB) is less than tSKEW1, then (FFA,FFB) may not change state until the
next (WCLKA,WCLKB) rising edge.
12. tSKEW1 is the minimum time between a rising (WCLKA,WCLKB) edge and a rising (RCLKA,RCLKB) edge to guarantee that (EFA,EFB) will go HIGH during the current clock
cycle. It the time between the rising edge of (WCLKA,WCLKB) and the rising edge of RCLK is less than tSKEW1, then (EFA,EFB) may not change state until the next
(RCLKA,RCLKB) rising edge.
Document #: 38-06005 Rev. *A
Page 7 of 23
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