CY7C4801_02 Datasheet, PDF (6/23 Pages) Cypress Semiconductor – 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs

CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Characteristics Over the Operating Range
Parameter
Description
f_S
t_A
t_CLK
t_CLKH
t_CLKL
t_DS
t_DH
t_ENS
t_ENH
t_RS
t_RSS
t_RSR
t_RSF
t_OLZ
t_OE
t_OHZ
t_WFF
t_REF
t_PAF
t_PAE
t_SKEW1
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width^[9]
Reset Set-Up Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low Z^[10]
Output Enable to Output Valid
Output Enable to Output in High Z^[10]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
Clock to Programmable Almost-Full Flag
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
t_SKEW2
Skew Time between Read Clock and Write
Clock for Almost-Empty Flag and Almost-Full
Flag
Notes:
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
7C48X1-10 7C48X1-15 7C48X1-25 7C48X1-35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
100
66.7
40
28.6 MHz
2
8
2 10 2 15 2 20 ns
10
15
25
35
ns
4.5
6
10
14
ns
4.5
6
10
14
ns
3.5
4
6
7
ns
0.5
1
1
2
ns
3.5
4
6
7
ns
0.5
1
1
2
ns
10
15
25
35
ns
8
10
15
20
ns
8
10
15
20
ns
10
15
25
35 ns
0
0
0
0
ns
3
7
3
8
3 12 3 15 ns
3
7
3
8
3 12 3 15 ns
8
10
15
20 ns
8
10
15
20 ns
8
10
15
20 ns
8
10
15
20 ns
5
6
10
12
ns
15
15
18
20
ns
Document #: 38-06005 Rev. *A
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