CY7C1541V18 Datasheet, PDF (7/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1541V18
CY7C1556V18
CY7C1543V18
CY7C1545V18
Pin Definitions (continued)
Pin Name
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/144M
NC/288M
V_REF
V_DD
V_SS
V_DDQ
IO
Pin Description
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
clock (K) of the QDR-II+. The timings for the echo clocks are shown in “Switching Characteristics”
on page 22.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ and Q_[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternately, this pin can be connected directly to V_DDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-
nected.
Input
DLL Turn Off-Active LOW. Connecting this pin to ground turns off the DLL inside the device.The
timings in the DLL turned off operation are different from those listed in this data sheet. For normal
operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device
behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a
frequency of up to 167 MHz with QDR-I timing.
Output TDO for JTAG.
Input
TCK pin for JTAG.
Input
TDI pin for JTAG.
Input
TMS pin for JTAG.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
Reference as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1541V18, CY7C1556V18, CY7C1543V18, and
CY7C1545V18 are synchronous pipelined Burst SRAMs
equipped with both a Read Port and a Write Port. The Read Port
is dedicated to read operations and the Write Port is dedicated
to write operations. Data flows into the SRAM through the Write
Port and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write Ports, the QDR-II+
completely eliminates the need to “turn-around” the data bus and
avoids any possible data contention, thereby simplifying system
design. Each access consists of four 8-bit data transfers in the
case of CY7C1541V18, four 9-bit data transfers in the case of
CY7C1556V18, four 18-bit data transfers in the case of
CY7C1543V18, and four 36-bit data transfers in the case of
CY7C1545V18, in two clock cycles.
Accesses for both ports are initiated on the Positive Input Clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D_[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q_[x:0]) outputs pass through output
registers controlled by the rising edge of the input clocks (K and
K) as well.
All synchronous control (RPS, WPS, BWS_[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1543V18 is described in the following sections. The same
basic descriptions apply to CY7C1541V18, CY7C1556V18, and
CY7C1545V18.
Read Operations
The CY7C1543V18 is organized internally as 4 arrays of 1M x
18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the Positive Input Clock (K). The
address presented to address inputs are stored in the Read
Address register. Following the next two K clock rise, the corre-
sponding lowest order 18-bit word of data is driven onto the
Q_[17:0] using K as the output timing reference. On the subse-
quent rising edge of K the next 18-bit data word is driven onto
the Q_[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q_[17:0]. The requested data is valid
0.45*ns from the rising edge of the input clock (K or K). In order
to maintain the internal logic, each read access must be allowed
to complete. Each read access consists of four 18-bit data words
Document Number: 001-05389 Rev. *E
Page 7 of 28