CY7C1541V18 Datasheet, PDF (22/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1541V18
CY7C1556V18
CY7C1543V18
CY7C1545V18
Switching Characteristics
Over the Operating Range ^{[22, 23]}
CY Consortium
Parameter Parameter
Description
t_POWER
t_CYC
t_KHKH
t_KH
t_KHKL
t_KL
t_KLKH
t_KHKH
t_KHKH
Setup Times
V_DD(Typical) to the First Access^[24]
K Clock Cycle Time
Input Clock (K/K) HIGH
Input Clock (K/K) LOW
K Clock Rise to K Clock Rise (rising edge to rising edge)
t_SA
t_SC
t_SCDDR
t_AVKH
t_IVKH
t_IVKH
t_SD
t_DVKH
Hold Times
Address Setup to K Clock Rise
Control Setup to K Clock Rise (RPS, WPS)
Double Data Rate Control Setup to Clock (K/K) Rise
(BWS₀, BWS_1, BWS₂, BWS₃)
D_[X:0] Setup to Clock (K/K) Rise
t_HA
t_HC
t_HCDDR
t_KHAX
t_KHIX
t_KHIX
t_HD
t_KHDX
Output Times
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
Double Data Rate Control Hold after Clock (K/K) Rise
(BWS₀, BWS_1, BWS₂, BWS₃)
D_[X:0] Hold after Clock (K/K) Rise
t_CO
t_DOH
t_CHQV
t_CHQX
K/K Clock Rise to Data Valid
Data Output Hold after Output K/K Clock Rise
(Active to Active)
t_CCQO
t_CQOH
t_CQD
t_CQDOH
t_CQH
t_CQHCQH
t_CHCQV
t_CHCQX
t_CQHQV
t_CQHQX
t_CQHCQL
t_CQHCQH
t_CHZ
t_CLZ
t_QVLD
t_CHQZ
t_CHQX1
t_CQHQVLD
K/K Clock Rise to Echo Clock Valid
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
Echo Clock High to Data Invalid
Output Clock (CQ/CQ) HIGH^[27]
CQ Clock Rise to CQ Clock Rise^[27]
(rising edge to rising edge)
Clock (K/K) Rise to High-Z (Active to High-Z)^{[25, 26]}
Clock (K/K) Rise to Low-Z^{[25, 26]}
Echo Clock High to QVLD Valid^[28]
375 MHz 333 MHz 300 MHz
Unit
Min Max Min Max Min Max
1
1
1
ms
2.66 8.40 3.0 8.40 3.3 8.40 ns
0.4 – 0.4
0.4 –
0.4 – 0.4
0.4 –
1.13 – 1.28 – 1.40 –
t_CYC
t_CYC
ns
0.4 – 0.4 – 0.4 – ns
0.4 – 0.4 – 0.4 – ns
0.28 – 0.28 – 0.28 – ns
0.28 – 0.28 – 0.28 – ns
0.4 – 0.4 – 0.4 – ns
0.4 – 0.4 – 0.4 – ns
0.28 – 0.28 – 0.28 – ns
0.28 – 0.28 – 0.28 – ns
– 0.45 – 0.45 – 0.45 ns
–0.45 – –0.45 – –0.45 – ns
– 0.45 – 0.45 – 0.45 ns
–0.45 – –0.45 – –0.45 – ns
0.2
0.2
0.2 ns
–0.2 – –0.2 – –0.2 – ns
0.88 – 1.03 – 1.15 – ns
0.88 – 1.03 – 1.15 – ns
– 0.45 – 0.45 – 0.45 ns
–0.45 – –0.45 – –0.45 – ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 ns
Notes
23. When a part with a maximum frequency above 300MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
24. This part has a voltage regulator internally; t_POWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can
be initiated.Hold to >V_IH or <V_IL.
25. t_CHZ, t_CLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
26. At any given voltage and temperature t_CHZ is less than t_CLZ and t_CHZ less than t_CO.
27. These parameters are extrapolated from the input timing parameters (t_KHKH-250ps, where 250ps is the internal jitter. An input jitter of 200ps(t_KCVAR) is already included
in the t_KHKH). These parameters are only guaranteed by design and are not tested in production.
28. t_QVLD spec is applicable for both rising and falling edges of QVLD signal.
Document Number: 001-05389 Rev. *E
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