English
Language : 

CY7C1541V18 Datasheet, PDF (21/28 Pages) Cypress Semiconductor – 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1541V18
CY7C1556V18
CY7C1543V18
CY7C1545V18
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range[15]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
ISB1 (x36) Automatic Power down
Current
Max VDD,
300 MHz
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC, Inputs Static
333 MHz
375 MHz
385
mA
395
410
AC Electrical Characteristics
Over the Operating Range[14]
Parameter
Description
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
Test Conditions
Min
VREF + 0.2
–0.24
Typ
Max
Unit
– VDDQ + 0.24 V
–
VREF – 0.2
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
5
pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
165 FBGA
Package
11.82
2.33
Unit
°C/W
°C/W
AC Test Loads and Waveforms
VREF
OUTPUT
Device
Under
Test
ZQ
(a)
0.75V
Z0 = 50Ω
RQ =
250Ω
VREF
RL = 50Ω
VREF = 0.75V
OUTPUT
Device
Under
Test ZQ
INCLUDING
JIG AND
SCOPE
VREF = 0.75V
0.75V
R = 50Ω
RQ =
250Ω
(b)
5 pF 0.25V
ALL INPUT PULSES[22]
1.25V
0.75V
Slew Rate = 2 V/ns
Note
22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse
levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of “AC Test Loads and Waveforms” on page 21.
Document Number: 001-05389 Rev. *E
Page 21 of 28