CY7C1410V18 Datasheet, PDF (7/23 Pages) Cypress Semiconductor – 36-Mbit QDR-II™ SRAM 2-Word Burst Architecture

PRELIMINARY
CY7C1410V18
CY7C1425V18
CY7C1412V18
CY7C1414V18
Pin Definitions (continued)
Pin Name
K
CQ
CQ
ZQ
DOFF
TDO
TCK
TDI
TMS
NC
NC/72M
NC/144M
NC/288M
V_REF
V_DD
V_SS
V_DDQ
I/O
Input-Clock
Echo Clock
Echo Clock
Input
Input
Output
Input
Input
Input
N/A
N/A
N/A
N/A
Input-
Reference
Power Supply
Ground
Power Supply
Pin Description
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q_[x:0] when in single clock mode.
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC Timing table.
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to V_DD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the
device. The timings in the DLL turned off operation will be different from those listed in
this data sheet. More details on this operation can be found in the application note, “DLL
Operation in the QDR-II.”
TDO for JTAG.
TCK pin for JTAG.
TDI pin for JTAG.
TMS pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1410V18, CY7C1425V18, CY7C1412V18 and
CY7C1414V18 are synchronous pipelined Burst SRAMs
equipped with both a Read port and a Write port. The Read
port is dedicated to Read operations and the Write port is
dedicated to Write operations. Data flows into the SRAM
through the Write port and out through the Read port. These
devices multiplex the address inputs in order to minimize the
number of address pins required. By having separate Read
and Write ports, the QDR-II completely eliminates the need to
“turn-around” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of two 8-bit data transfers in the case of
CY7C1410V18, two 9-bit data transfers in the case of
CY7C1425V18,two 18-bit data transfers in the case of
CY7C1412V18 and two 36-bit data transfers in the case of
CY7C1414V18, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D_[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q_[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS_[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1412V18 is described in the following sections. The
same basic descriptions apply to CY7C1410V18
CY7C1425V18 and CY7C1414V18.
Read Operations
The CY7C1412V18 is organized internally as 2 arrays of
1Mx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
Document #: 38-05592 Rev. **
Page 7 of 23