CY8C25122_05 Datasheet, PDF (67/151 Pages) Cypress Semiconductor – Mixed-Signal Array with On-board Controller

Digital PSoC Blocks
9.5.6.3 Inputs
A baud-rate clock running at 8 times the desired input bit
rate is selected by the clock-input multiplexer The serial
data input and clock input are controlled by the Input
Register (DCA04IN-DCA07IN).
9.5.6.4
None.
Outputs
9.5.6.5 Interrupts
The function can be configured to generate an interrupt
on RXREGFULL (Receive Register Full) status (Data
Register 2 is full)
9.5.6.6 Usage Notes
1. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets all status bits to 0 with
the exception of RX Reg Full. Reading Data Regis-
ter 2 (Receive Data Register) clears the RX Reg Full
status.
2. Using Interrupts
RX Reg Full status generates an interrupt but the
Receive Data Register (Data Register 2) must be
read to clear the RX Reg Full status. If this registers
is not read in the interrupt routine, the status will not
be cleared and further interrupts will be suppressed.
If the stop bit in a transmitted byte is missing, the
receiver will declare a framing error. Once this
occurs, this missing stop bit can be interpreted as
the start bit of the next byte, which will produce
another framing error.
9.5.7 Universal Asynchronous Transmitter
9.5.7.1 Summary
The Universal Asynchronous Transmitter implements the
output half of a basic 8-bit UART. Start and Stop bits are
generated. Parity bit generation and type are config-
urable features. This function requires a Digital Commu-
nications Type PSoC block. It cannot be chained for
longer data words.
9.5.7.2 Registers
When Data Register 0 is empty and a new byte has been
written to Data Register 1, the function transfers the byte
to Data Register 0 and shifts it out along with a start bit,
optionally a parity bit and a stop bit. Once Data Register
0 is loaded with the byte to shift out, Data Register 0 can
be immediately loaded with the next byte to transmit, act-
ing as a 1 byte transmit buffer. Data Register 2 is not
used by this function. The PSoC block’s Control Register
0 (DCA04CR0-DCA07CR0) configures the parity type
and enable. It also provides status information to enable
detection of transmission complete.
9.5.7.3 Inputs
A baud-rate clock running at 8 times the desired output
bit rate is selected by the clock-input multiplexer con-
trolled by the PSoC block Input Register (DCA04IN-
DCA07IN). The Data Input multiplexer is ignored by this
function.
9.5.7.4 Outputs
The transmitter’s serial data output appears at the PSoC
block output and may be driven onto one of the Global
Output bus lines. The PSoC block Output Register
(DCA04OU-DCA07OU) controls output options.
9.5.7.5 Interrupts
If enabled, the function will generate an interrupt when
the TX Reg Empty status is set (Data Register 1 is
empty). Optionally, the interrupt can be set to TX Com-
plete status, which indicates all bits of a given byte have
been sent, including framing bits. This option is selected
based on the Mode[1] bit in the Function Register.
9.5.7.6 Usage Notes
1. TX Reg Empty Interrupt
An initial byte must be written to the TX Data Regis-
ter (Data Register 1) to enable subsequent TX Reg
Empty status interrupts. This does not apply if the
TX Complete interrupt source is selected.
2. Reading the Status
Reading Control Register 0, which contains the sta-
tus bits, automatically resets the status bits to 0,
May 17, 2005
Document #: 38-12010 CY Rev. *C
67