CY8C25122_05 Datasheet, PDF (114/151 Pages) Cypress Semiconductor – Mixed-Signal Array with On-board Controller

CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
11.3 Reset
11.3.1 Overview
The microcontroller supports two types of resets. When
reset is initiated, all registers are restored to their default
states and all interrupts are disabled.
Reset Types: Power On Reset (POR), External Reset
(X_res), and Watchdog Reset (WDR).
The occurrence of a reset is recorded in the Status and
Control Register (CPU_SCR). Bits within this register
record the occurrence of POR and WDR Reset respec-
tively. The firmware can interrogate these bits to deter-
mine the cause of a reset.
The microcontroller resumes execution from ROM
address 0x0000 after a reset. The internal clocking mode
is active after a reset, until changed by user firmware. In
addition, the Sleep / Watchdog Timer is reset to its mini-
mum interval count.
Important: The CPU clock defaults to divide by 8 mode
at POR to guarantee operation at the low Vcc that might
be present during the supply ramp.
Table 94: Processor Status and Control Register
Bit #
7
6
5
4
POR
0
0
0
1
Read/
Write
R
--
R/C¹
R/C¹
Bit Name
IES
Reserved WDRS
PORS
3
0
RW
Sleep
2
1
0
0
--
--
Reserved Reserved
0
0
RW
Stop
Bit 7: IES Global interrupt enable status from CPU Flag register
0 = Global interrupts disabled
1 = Global interrupts enabled
Bit 6: Reserved
Bit 5: WDRS
WDRS is set by the CPU to indicate that a Watchdog Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No WDR
1 = A WDR event has occurred
Bit 4: PORS
PORS is set by the CPU to indicate that a Power On Reset event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit
0 = No POR
1 = A POR event has occurred. (Note that WDR events will not occur until this bit is cleared)
Bit 3: Sleep Set by the user to enable CPU sleep state. CPU will remain in sleep mode until any interrupt is pending
0 = Normal operation
1 = Sleep
Bit 2: Reserved
Bit 1: Reserved
Bit 0: Stop Set by the user to halt the CPU. The CPU will remain halted until a reset (WDR or POR) has taken place
0 = Normal CPU operation
1 = CPU is halted (not recommended)
1. C = Clear
Status and Control Register (CPU_SCR, Address = Bank 0/1, FFh)
114
Document #: 38-12010 CY Rev. *C
May 17, 2005