CY8C25122_05 Datasheet, PDF (28/151 Pages) Cypress Semiconductor – Mixed-Signal Array with On-board Controller

CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet
4.3 Register Bank 1 Map
Table 27: Bank 1
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
DBA00FN
DBA00IN
DBA00OU
Reserved
DBA01FN
DBA01IN
DBA01OU
Reserved
DBA02FN
DBA02IN
DBA02OU
Reserved
DBA03FN
DBA03IN
DBA03OU
Reserved
DCA04FN
DCA04IN
DCA04OU
Reserved
DCA05FN
DCA05IN
DCA05OU
Reserved
DCA06FN
DCA06IN
DCA06OU
Reserved
DCA07FN
DCA07IN
DCA07OU
Reserved
00h 32
01h 33
02h 33
03h 34
04h 32
05h 33
06h 33
07h 34
08h 32
09h 33
0Ah 33
0Bh 34
0Ch 32
0Dh 33
0Eh 33
0Fh 34
10h 32
11h 33
12h 33
13h 34
14h 32
15h 33
16h 33
17h 34
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h 50
21h 51
22h 53
23h
24h 50
25h 51
26h 53
27h
28h 50
29h 51
2Ah 53
2Bh
2Ch 50
2Dh 51
2Eh 53
2Fh
30h 50
31h 51
32h 53
33h
34h 50
35h 51
36h 53
37h
38h 50
39h 51
3Ah 53
3Bh
3Ch 50
3Dh 51
3Eh 53
3Fh
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
RW CLK_CR0
RW CLK_CR1
RW ABF_CR
AMD_CR
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW ACA00CR0
RW ACA00CR1
ACA00CR2
RW Reserved
RW ACA01CR0
RW ACA01CR1
ACA01CR2
RW Reserved
RW ACA02CR0
RW ACA02CR1
ACA02CR2
RW Reserved
RW ACA03CR0
RW ACA03CR1
ACA03CR2
40h
ASA10CR0
41h
ASA10CR1
42h
ASA10CR2
43h
ASA10CR3
44h
ASB11CR0
45h
ASB11CR1
46h
ASB11CR2
47h
ASB11CR3
48h
ASA12CR0
49h
ASA12CR1
4Ah
ASA12CR2
4Bh
ASA12CR3
4Ch
ASB13CR0
4Dh
ASB13CR1
4Eh
ASB13CR2
4Fh
ASB13CR3
50h
ASB20CR0
51h
ASB20CR1
52h
ASB20CR2
53h
ASB20CR3
54h
ASA21CR0
55h
ASA21CR1
56h
ASA21CR2
57h
ASA21CR3
58h
ASB22CR0
59h
ASB22CR1
5Ah
ASB22CR2
5Bh
ASB22CR3
5Ch
ASA23CR0
5Dh
ASA23CR1
5Eh
ASA23CR2
5Fh
ASA23CR3
60h 76 RW
61h 77 RW
62h 106 W
63h 107 RW
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h 82 RW
72h 83 RW
73h 84 RW
74h
75h 82 RW
76h 83 RW
77h 84 RW
78h
79h 82 RW
7Ah 83 RW
7Bh 84 RW
7Ch
7Dh 82 RW
7Eh 83 RW
7Fh 84 RW
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
88 RW
90 RW
92 RW
93 RW
95 RW
97 RW
99 RW
100 RW
88 RW
90 RW
92 RW
93 RW
95 RW
97 RW
99 RW
100 RW
95 RW
97 RW
99 RW
100 RW
88 RW
90 RW
92 RW
93 RW
95 RW
97 RW
99 RW
100 RW
88 RW
90 RW
92 RW
93 RW
OSC_CR0
OSC_CR1
Reserved
VLT_CR
Reserved
Reserved
Reserved
Reserved
IMO_TR
ILO_TR
BDG_TR
ECO_TR
CPU_SCR
1. Read/Write access is bit-specific or varies by function. See register.
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h 40 RW
E1h 40 RW
E2h
E3h 118 RW
E4h
E5h
E6h
E7h
E8h 35 W
E9h 36 W
EAh 120 W
EBh 37 W
ECh
EDh
EEh
EFh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh 114 ¹
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Document #: 38-12010 CY Rev. *C
May 17, 2005