CY7C601XX_09_09 Datasheet, PDF (60/68 Pages) Cypress Semiconductor – enCoRe II Low Voltage Microcontroller

CY7C601xx, CY7C602xx
20.2 AC Characteristics
Parameter
Description
Clock
T_ECLKDC External Clock Duty Cycle
T_ECLK2
External Clock Frequency
F_IMO
Internal Main Oscillator Frequency
F_ILO
Internal Low Power Oscillator
GPIO Timing
T_{R_GPIO} Output Rise Time
T_{F_GPIO} Output Fall Time
SPI Timing
T_SMCK
T_SSCK
T_SCKH
T_SCKL
T_MDO
T_MDO1
SPI Master Clock Rate
SPI Slave Clock Rate
SPI Clock High Time
SPI Clock Low Time
Master Data Output Time^[6]
Master Data Output Time,
First bit with CPHA = 0
T_MSU
T_MHD
T_SSU
T_SHD
T_SDO
T_SDO1
Master Input Data Setup time
Master Input Data Hold time
Slave Input Data Setup Time
Slave Input Data Hold Time
Slave Data Output Time
Slave Data Output Time,
First bit with CPHA = 0
T_SSS
T_SSH
Slave Select Setup Time
Slave Select Hold Time
Conditions
Min Typical Max
45
55
1
24
With proper trim values loaded^[5]
18.72
26.4
With proper trim values loaded^[5] 15.0001
50.0
Measured between 10 and 90% Vdd
50
and Vreg with 50 pF load
Measured between 10 and 90% Vdd
15
and Vreg with 50 pF load
F_CPUCLK/6
2
2.2
High for CPOL = 0, Low for CPOL = 1 125
Low for CPOL = 0, High for CPOL = 1 125
SCK to data valid
–25
50
Time before leading SCK edge
100
50
50
50
50
SCK to data valid
100
Time after SS LOW to data valid
100
Before first SCK edge
150
After last SCK edge
150
Figure 20-1. Clock Timing
T_CH
T_CYC
Unit
%
MHz
MHz
KHz
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLOCK
T_CL
Notes
5. Refer to Clocking on page 21 for details on loading proper trim values.
6. In Master mode, first bit is available 0.5 SPICLK cycle before Master clock edge is available on the SCLK pin.
Document 38-16016 Rev. *F
Page 60 of 68
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