Z9973 Datasheet, PDF (6/9 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9973
Maximum Ratings^[3]
Maximum Input Voltage Relative to V_SS: ............ V_SS – 0.3V
Maximum Input Voltage Relative to V_DD: ............. V_DD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature: ................................ –40°C to +85°C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V_IN and V_OUT should be constrained to
the range:
V_SS < (V_IN or V_OUT) < V_DD .
Unused inputs must always be tied to an appropriate logic
voltage level (either V_SS or V_DD).
DC Parameters (V_DD = 2.9V to 3.6V, V_DDC = 3.3V ±10%, T_A = –40°C to +85°C)
Parameter
Description
Conditions
Min. Typ. Max. Unit
V_IL
V_IH
V_PP
V_CMR
I_IL
I_IH
V_OL
V_OH
I_DDQ
I_DDA
I_DD
C_IN
Input LOW Voltage
Input HIGH Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range PECL_CLK^[9]
Input Low Current^[10]
Input High Current^[10]
Output Low Voltage^[11]
Output High Voltage^[11]
I_OL = 20 mA
I_OH = –20 mA
Quiescent Supply Current
PLL Supply Current
Dynamic Supply Current
Input Pin Capacitance
V_DD only
QA and QB @ 60 MHz,
QC @ 120 MHz, C_L = 30 pF
QA and QB @ 25 MHz,
QC @ 50 MHz, C_L = 30 pF
V_SS
0.8
V
2.0
V_DD
V
300
1000 mV
V_DD – 2.0
V_DD – 0.6 V
–120
µA
120
µA
0.5
V
2.4
V
10
15
mA
15
20
mA
225
mA
125
4
pF
AC Parameters (V_DD = 2.9V to 3.6V, V_DDC = 3.3V ±10%, T_A = –40°C to +85°C) ^[4]
Parameter
Description
Conditions
Min. Typ.
Tr / Tf
TCLK Input Rise / Fall
Fref
Reference Input Frequency
Note 5
FrefDC
Reference Input Duty Cycle
25
Fvco
PLL VCO Lock Range
200
Tlock
Maximum PLL Lock Time
Tr / Tf
Output Clocks Rise/Fall Time^[6]
0.8V to 2.0V
0.15
Notes:
3. The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
5. Maximum and minimum input reference is limited by VC0 lock range.
6. Outputs loaded with 30 pF each.
Max. Units
3.0
ns
Note 5 MHz
75
%
480 MHz
10
ms
1.2
ns
Document #: 38-07089 Rev. *D
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