Z9973 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9973
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Features
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
Block Diagram
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
TCLK0 ₀
TCLK1 1
TCLK_SEL
FB_IN
Phase
Detector
VCO
0
1
LPF
FB_SEL2
MR#/OE
Power-On
Reset
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
Data Generator
0
/2 1
SCLK
SDATA
Output Disable ₁₂
Circuitry
INV_CLK
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
DQ
Sync
Frz
Table 1. Frequency Table^[1]
VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0
F_VC0
0
0
0
0
8x
0
0
0
1
12x
0
0
1
0
16x
0
0
1
1
20x
0
1
0
0
16x
0
1
0
1
24x
0
1
1
0
32x
0
1
1
1
40x
1
0
0
0
4x
1
0
0
1
6x
1
0
1
0
8x
1
0
1
1
10x
1
1
0
0
8x
1
1
0
1
12x
1
1
1
0
16x
1
1
1
1
20x
Note:
1. x = the reference input frequency, 200 MHz < F_VCO < 480 MHz.
.
Pin Configuration
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
VSS
MR#/OE
SCLK
SDATA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
VDD
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
34
7
Z9973 ³³
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
VSS
QB0
VDDC
QB1
VSS
QB2
VDDC
QB3
FB_IN
VSS
FB_OUT
VDDC
FB_SEL0
SYNC
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07089 Rev. *D
Revised December 21, 2002