W48C111-17 Datasheet, PDF (6/7 Pages) Cypress Semiconductor – 100-MHz Mobile Motherboard System Clock

PRELIMINARY
W48C111-17
REF Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
f_ST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
3
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used for
40
determining series termination value.
Unit
MHz
V/ns
V/ns
%
ms
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
f_D
Deviation from 48 MHz
m/n
PLL Ratio
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to fre-
quency stabilization.
Average value during switching transition. Used
for determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
48.008
+167
57/17
0.5
2
0.5
2
45
55
3
40
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
Ordering Information
Ordering Code
Freq. Mask
Code
W48C111
-17
Package
Name
H
Package Type
28-pin SSOP (209 mils)
Document #:38-00843
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