W48C111-17 Datasheet, PDF (2/7 Pages) Cypress Semiconductor – 100-MHz Mobile Motherboard System Clock

PRELIMINARY
W48C111-17
Pin Definitions
Pin Name
CPU0:1
Pin
No.
24, 23
PCI1:5
PCI_F
5, 7, 8, 10,
11
4
48MHz
16
CPU_STOP#
18
PCI_STOP#
19
REF
26
SEL100/66#
15
X1
1
X2
2
PWR_DWN#
17
VDDQ3
VDDQ2
GND
6, 9, 13, 21,
27
25
3, 12, 14, 20,
22, 28
Pin
Type
O
O
O
O
I
I
O
I
I
I
I
P
P
G
Pin Description
CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ2. Frequency of signals is set by SEL100/66# input.
PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled
by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied
to VDDQ3.
Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the
PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage
swing is controlled by voltage applied to VDDQ3.
48-MHz Output: Fixed clock output at 48 MHz. Output voltage swing is controlled by
voltage applied to VDDQ3.
CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW
after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH,
clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency).
PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH
and causes them to remain at logic 0 when LOW. The PCI_STOP signal is latched
on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle.
Fixed 14.318-MHz Output: Used for various system applications. Output voltage
swing is controlled by voltage applied to VDDQ3.
Frequency Selection Inputs: Select power-up default CPU clock frequency as
shown in Table 1 on page 1.
Crystal Connection or External Reference Frequency Input: This pin can either
be used as a connection to a crystal or to a reference signal.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power-Down Control: When this input is LOW, device goes into a low-power stand-
by condition. All outputs are held LOW. CPU and PCI clock outputs are stopped LOW
after completing a full clock cycle (2–3 CPU clock cycle latency). When brought
HIGH, CPU and PCI outputs start with a full clock cycle at full operating frequency
(3 ms maximum latency).
Power Connection: Connected to 3.3V supply.
Power Connection: Power supply for CPU0:1 output buffer. Connected to 2.5V.
Ground Connection: Connect all ground pins to the common system ground plane.
2