W48C111-17 Datasheet, PDF (5/7 Pages) Cypress Semiconductor – 100-MHz Mobile Motherboard System Clock

PRELIMINARY
W48C111-17
AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%,V_DDQ2 = 2.5V± 5%, f_XTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15
15.5 10
10.5 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Time Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
200
imum difference of cycle time between
two adjacent cycles.
250 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
175 ps
f_ST
Frequency Stabiliza- Assumes full supply voltage reached
3
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching transi-
13.5
tion. Used for determining series termi-
nation value.
13.5
Ω
PCI Clock Outputs, PCI1:5 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
Description
t_P
Period
t_H
High Time
t_L
Low Time
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
t_JC
Jitter, Cycle-to-Cycle
t_SK
Output Skew
t_O
CPU to PCI Clock Skew
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
30
12
12
1
4
1
4
45
55
250
500
1.5
4
3
30
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
5