W256 Datasheet, PDF (6/9 Pages) Cypress Semiconductor – 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

Switching Waveforms (continued)
SDRAM Buffer HH and LL Propagation Delay
INPUT
1.5V
OUTPUT
1.5V
t₆
t₇
Figure 1 shows the differential clock directly terminated by a
120 Ω resistor.
V_CC
Device _Out
Under
Test
Out
V_CC
) ^60Ω
) ^60Ω
W256
VTR
R_T =120Ω
VCP
Receiver
Figure 1. Differential Signal Using Direct Termination Resistor
Document #: 38-07256 Rev. *C
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