W256 Datasheet, PDF (5/9 Pages) Cypress Semiconductor – 12 Output Buffer for 2 DDR and 3 SRAM DIMMS

Switching Characteristics^[4]
Parameter
Name
Test Conditions
–
Operating Frequency
–
Duty Cycle^[4,5] = t₂ ÷ t₁
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
t₃
SDRAM Rising Edge Rate^[4]
Measured between 0.4V and 2.4V
t₄
SDRAM Falling Edge Rate^[4]
Measured between 2.4V and 0.4V
t_3d
DDR Rising Edge Rate^[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
t_4d
DDR Falling Edge Rate^[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
t₅
Output to Output Skew^[4]
All outputs equally loaded
t₆
Output t4o Output Skew for
SDRAM^[2]
All outputs equally loaded
t₇
SDRAM Buffer HH Prop. Delay^[4] Input edge greater than 1 V/ns
t₈
SDRAM Buffer LLProp. Delay^[4] Input edge greater than 1 V/ns
Switching Waveforms
Duty Cycle Timing
t₁
t₂
Min.
66
IN_DC
–5%
1.0
1.0
0.5
0.5
5
5
W256
Typ.
Max.
180
IN_DC +5%
Unit
MHz
%
2.50
2.50
1.50
V/ns
V/ns
V/ns
1.50 V/ns
100
ps
150
ps
10
ns
10
ns
All Outputs Rise/Fall Time
2.4V
OUTPUT _0.4V
t₃
Output-Output Skew
2.4V
0.4V
t₄
3.3V
0V
OUTPUT
OUTPUT
t₅
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Document #: 38-07256 Rev. *C
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