W211B Datasheet, PDF (6/16 Pages) Cypress Semiconductor – FTG for 440BX, VIA Apollo Pro-133, and ProMedia

PRELIMINARY
W211B
Writing Data Bytes
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 5 gives the bit formats for registers located in Data
Bytes 0–7.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 5. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s) Pin No.
Data Byte 0
7
--
Pin Name
--
Control Function
(Reserved)
0
1
Default
--
--
0
6
--
5
--
4
--
--
SEL_2
--
SEL_1
--
SEL_0
See Table 6
0
See Table 6
0
See Table 6
0
3
--
2
--
1
--
--
Hardware/Software Frequency Select
Hardware
Software
0
--
SEL_4
See Table 6
1
--
SEL_3
See Table 6
0
0
--
Data Byte 1
7
--
--
--
(Reserved)
Normal
--
Three-stated
0
--
0
6
--
5
--
4
--
--
(Reserved)
--
(Reserved)
--
(Reserved)
--
--
0
--
--
0
--
--
0
3
40 SDRAM_12 Clock Output Disable
2
--
--
(Reserved)
1
43
CPU1 Clock Output Disable
Low
Active
1
--
--
0
Low
Active
1
0
44
Data Byte 2
7
--
CPU_F Clock Output Disable
--
(Reserved)
Low
Active
1
--
--
0
6
7
5
--
4
13
PCI0
--
PCI5
Clock Output Disable
(Reserved)
Clock Output Disable
Low
Active
1
--
--
0
Low
Active
1
3
12
2
11
1
10
PCI4
PCI3
PCI2
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Active
1
Low
Active
1
Low
Active
1
0
8
Data Byte 3
7
--
PCI1
Clock Output Disable
--
(Reserved)
Low
Active
1
--
--
0
6
-- SEL_48MHz SEL 48MHz as the output frequency for
24 MHz
24_48MHz
5
26
48MHz Clock Output Disable
Low
4
25 24_48MHz Clock Output Disable
Low
48 MHz
0
Active
1
Active
1
3
--
--
(Reserved)
2 21, 20, SDRAM8:11 Clock Output Disable
18, 17
--
--
0
Low
Active
1
1 32, 31, SDRAM4:7 Clock Output Disable
29, 28
Low
Active
1
Document #: 38-07174 Rev. **
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