W211B Datasheet, PDF (2/16 Pages) Cypress Semiconductor – FTG for 440BX, VIA Apollo Pro-133, and ProMedia

PRELIMINARY
W211B
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
CPU_F
44
O Free-running CPU Clock: Output voltage swing is controlled by the voltage applied to
VDDQ2. See Table 2 and Table 6 for detailed frequency information.
CPU1
43
O CPU Clock Output 1: This CPU clock output is controlled by the CPU_STOP# and
PWRDWN# control pin. Output voltage swing is controlled by voltage applied to VDDQ2.
PCI2:5
10, 11, 12, 13
O PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the
PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface,
see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to
VDDQ3.
PCI1/FS1
8
I/O Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs
or through serial input interface. This output is controlled by the PWRDWN# input. This pin
also serves as a power-on strap option to determine device operating frequency as described
in Table 2.
PCI0/MODE
7
I/O Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through
serial input interface, see Table 2 and Table 6. This output is controlled by the PWRDWN#
input. This pin also serves as a power-on strap option to determine the function of pin 2, see
Table 1 for details.
PWRDWN#
41
I PWRDWN# input: LVTTL-compatible input that places the device in power-down mode
when held LOW.
IOAPIC
47
O IOAPIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage swing is
controlled by VDDQ2. This output is disabled when PWRDWN# is set LOW.
48MHz/FS2
26
I/O 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard
PC systems, this output can be used as the reference for the Universal Serial Bus host
controller. This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 2.
24_48MHz/
FS3
25
I/O 24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can be used
as the clock input for a Super I/O chip. The output frequency is controlled by Configuration
Byte 3 bit[6]. The default output frequency is 48 MHz. This pin also serves as a power-on
strap option to determine device operating frequency as described in Table 2.
REF1/FS0
46
I/O Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin
also serves as a power-on strap option to determine device operating frequency as described
in Table 2. Upon power-up, FS0 input will be latched which will set clock frequencies as
described in Table 2.
REF0/
2
CPU_STOP#
I/O Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE
pin. When CPU_STOP# input is asserted LOW, it will disable CPU1 output and drive it to
logic 0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output
clock.
SDRAMIN
15
I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs
(SDRAM0:12).
SDRAM0:12
38, 37, 35, 34, 32,
31, 29, 28, 21, 20,
18, 17, 40
O Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided
at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when
PWRDWN# input is set LOW.
SCLK
24
I Clock pin for SMBus circuitry.
SDATA
23
I/O Data pin for SMBus circuitry.
X1
4
I Crystal Connection or External Reference Frequency Input: This pin has dual functions.
It can be used as an external 14.318-MHz crystal connection or as an external reference
frequency input.
X2
5
I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
VDDQ3
1, 6, 14, 19, 27, P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs,
30, 36
reference outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply.
VDDQ2
42, 48
P Power Connection: Power supply for IOAPIC, CPU_F, and CPU1 output buffers, connect
to 2.5V or 3.3V.
GND
3, 9, 16, 22, 33, 39, _{G Ground Connections: Connect all ground pins to the common system ground plane.}
45
Document #: 38-07174 Rev. **
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