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W211B Datasheet, PDF (1/16 Pages) Cypress Semiconductor – FTG for 440BX, VIA Apollo Pro-133, and ProMedia
PRELIMINARY
W211B
FTG for 440BX, VIA Apollo Pro-133, and ProMedia
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Single-chip system frequency synthesizer for 440BX,
VIA Apollo Pro-133, and ProMedia
• Supports Intel® Pentium® II and Cyrix class processors
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Supports frequencies up to 200 MHz
• SMBus interface for programming
• Power management control inputs
• Available in 48-pin SSOP
• SDRAM Range = 66 MHz to 133 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: .......................................... 250 ps
CPU to CPU Output Skew: ......................................... 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: .................................................................... 3.3V±5%
VDDQ2: .................................................................... 2.5V±5%
SDRAMIN to SDRAM0:12 Delay:........................ 4.5 – 6.0 ns
Table 1. Mode Input Table
Mode
Pin 2
0
CPU_STOP#
1
REF0
Table 2. Pin Selectable Frequency
Input Address
CPU_F, PCI_F, Spread
FS3 FS2 FS1 FS0 CPU1 (MHz) 1:5 (MHz) Spectrum
1111
133.3
33.3
±0.5%
1110
75
37.5
OFF
1101
100.2
33.3
±0.5%
1100
66.8
33.4
±0.5%
1011
79
39.5
OFF
1010
110
36.7
OFF
1001
115
38.3
OFF
1000
120
30
OFF
0111
133.3
33.3
–0.5%
0110
83
27.7
OFF
0101
100.2
33.3
–0.5%
0100
66.8
33.4
–0.5%
0011
122
30.5
–0.5%
0010
129
32.3
OFF
0001
138
34.5
OFF
0000
95
31.7
–0.5%
Block Diagram
X1
X2
XTAL
OSC
PLL Ref Freq
I/O Pin
Control
PWRDWN#
PLL 1
Stop
Clock
Control
÷2,3,4
SDATA
SCLK
SMBus
Logic
PLL2
÷2
SDRAMIN
VDDQ3
Pin Configuration[1]
REF0/(CPU_STOP#)
REF1/FS0
CPU_F
CPU1
VDDQ3
PCI0/MODE
PCI1/FS1
PCI2
PCI3
PCI4
PCI5
VDDQ3 1
REF0/(CPU_STOP#) 2
GND 3
X1 4
X2 5
VDDQ3 6
PCI0/MODE 7
PCI1/FS1* 8
GND 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
VDDQ3 14
SDRAMIN 15
GND 16
SDRAM11 17
SDRAM10 18
VDDQ3 19
SDRAM9 20
SDRAM8 21
GND 22
{ SMBus SDATA 23
SCLK 24
48 VDDQ2
47 IOAPIC
46 REF1/FS0*
45 GND
44 CPU_F
43 CPU1
42 VDDQ2
41 PWRDWN#
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS2*
25 24_48MHz/FS3^
VDDQ3
48MHz/FS2
24_48MHz/FS3
VDDQ3
SDRAM0:12
13
Note:
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH. Pin function with parentheses determined by MODE pin
resistor strapping. Unlike other I/O pins, input FS3 has an internal
pull-down resistor.
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07174 Rev. **
Revised September 25, 2001