W167B Datasheet, PDF (6/18 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum FTG for Pentium II Platforms

PRELIMINARY
W167B
Serial Data Interface
The W167B features a two-pin, serial data interface that can
be used to configure internal register settings that control par-
ticular device functions. Upon power-up, the W167B initializes
with default register settings, therefore the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 2 summarizes the control functions of
the serial data interface.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused SDRAM DIMM socket or PCI
slot.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections. Frequen-
cy is changed in a smooth and controlled fashion.
For alternate CPU devices, and power man-
agement options. Smooth frequency transi-
tion allows CPU frequency change under nor-
mal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation with X1 input,
internal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Operation
Data is written to the W167B in ten bytes of eight bits each. Bytes are written in the order shown in Table 3.
Table 3. Byte Writing Sequence
Byte Sequence Byte Name Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W167B to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W167B is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Don’t Care
Unused by the W167B, therefore bit values are ignored (don’t care). This
Code
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the W167B, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
4
Data Byte 0
Refer to Table 4 The data bits in these bytes set internal W167B registers that control
5
Data Byte 1
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
6
Data Byte 2
control functions, refer to Table 4, Data Byte Serial Configuration Map.
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
6