W167B Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum FTG for Pentium II Platforms

PRELIMINARY
W167B
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• Three copies of CPU outputs selectable frequency
• Three copies of 3V66 selectable frequency output at
3.3V
• Ten copies of PCI clocks (selectable frequency), 3.3V
• One double strength 14.318-MHz reference output at
3.3V
• One copy of 48-MHz USB clock
• One copy of selectable 24-/48-MHz for SIO
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Three copies of IOAPIC
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... V_DDQ2 = 2.5V±5%
V_DDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:8 Pin to Pin Skew: .............................................. 500 ps
Block Diagram
X1
XTAL
X2
OSC
VDDQ3
REF2X
VDDQ2
CPU_[0:2]
3
SEL133/100#
PLL 1
÷2
÷2/÷1.5
PWRDWN#
÷2
Power
Down
Logic
÷2
PLL2
SDATA
÷2
Serial
SCLK
Logic
CPUdiv2
VDDQ3
3V66_[0:2]
3
PCI0/SEL2*
PCI1/SEL1*
PCI_[2:9]
8
VDDQ2
IOAPIC[0:2]
3
QVD# DQ3
48MHz/SEL0*
SIO/24_48#MHz
Duty Cycle: ................................................................ 45/55%
Spread Spectrum Modulation:................................... ±0.25%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–4.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/
CPU 3V66 PCI IOAPIC
100# SEL2 SEL1 SEL0 MHz MHz MHz MHz
1
1
1
1 133.3 66.7 33.3 16.7
1
1
1
0 138 69 34.5 17.3
1
1
0
1 143 71.5 35.8 17.9
1
1
0
0 148 74 37 18.5
1
0
1
1 150 75 37.5 18.8
1
0
1
0 152.5 76.3 38.1 19.1
1
0
0
1 155 77.5 38.8 19.4
1
0
0
0 160 80 40 20
0
1
1
1 100.2 66.8 33.4 16.7
0
1
1
0 105 70 35 17.5
0
1
0
1 114 76 38 19
0
1
0
0 120 80 40 20
0
0
1
1 66.8 66.8 33.4 16.7
0
0
1
0 124 82.7 41.3 20.7
0
0
0
1 128.5 64.3 32.1 16.1
0
0
0
0 133.9 67 33.5 16.7
Pin Configuration^[1]
IOAPIC2 1
REF2X 2
VDDQ3 3
X1 4
X2 5
GND 6
SEL2*/PCI0 7
SEL1*/PCI1 8
VDDQ3 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
GND 14
PCI6 15
PCI7 16
VDDQ3 17
PCI8 18
PCI9 19
GND 20
3V66_0 21
3V66_1 22
3V66_2 23
VDDQ3 24
48 GND
47 _VDDQ2
46 IOAPIC0
45 IOAPIC1
44 _GND
43 VDDQ2
42 _CPUdiv2
41 _GND
40 _VDDQ2
39 CPU2
38 _GND
37 _VDDQ2
36 _CPU1
35 _CPU0
34 SDATA
33 VDDQ3
32 GND
31 PWRDN#*
30 SCLK
29 VDDQ3
28 SIO/24_48#MHz*
27 48MHz/SEL0*
26 GND
25 SEL133/100#
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
Direct Rambus is a trademark of Rambus, Inc. Pentium is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
November 2, 1999