W167B Datasheet, PDF (10/18 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum FTG for Pentium II Platforms

PRELIMINARY
W167B
How To Use the Serial Data Interface
Electrical Requirements
Figure 5 illustrates electrical characteristics for the serial inter-
face bus used with the W167B. Devices send data over the bus
with an open drain logic output that can (a) pull the bus line
LOW, or (b) let the bus default to logic 1. The pull-up resistors
on the bus (both clock and data lines) establish a default logic
1. All bus devices generally have logic inputs to receive data.
Although the W167B is a receive-only device (no data write-
back capability), it does transmit an “acknowledge” data pulse
after each byte is received. Thus, the SDATA line can both
transmit and receive data.
The pull-up resistor should be sized to meet the rise and fall
times specified in AC parameters, taking into consideration to-
tal bus line capacitance.
VDD
VDD
SERIAL BUS DATA LINE
SERIAL BUS CLOCK LINE
CLOCK IN
CLOCK OUT
SDCLK
DATA IN
N DATA OUT
~ 2kΩ
~ 2kΩ
SDATA
N
CLOCK IN
SCLOCK
DATA IN
DATA OUT
SDATA
N
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
Figure 5. Serial Interface Bus Electrical Characteristics
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