W161 Datasheet, PDF (6/9 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum FTG for Pentium II Platforms

PRELIMINARY
W161
PCI Clock Outputs, PCI0:9 (Lump Capacitance Test Load = 30 pF
Parameter
Description
t_P
Period
t_H
High Time
t_L
Low Time
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
t_JC
Jitter, Cycle-to-Cycle
Test Condition/Comments
Measured on rising edge at 1.5V^[9]
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
t_SK
Output Skew
Measured on rising edge at 1.5V.
t_O
3V66 to PCI Clock Skew Covers all 3V66/PCI outputs. Measured on rising
edge at 1.5V. 3V66 leads PCI output.
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold
from power-up. Short cycles exist prior to frequency
start)
stabilization.
Z_o
AC Output Impedance Average value during switching transition. Used for
determining series termination value.
Min.
30
12
12
1
1
45
1.5
Typ.
15
Max.
4
4
55
500
500
3
3
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
REF Clock Outputs, REF0:1 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Frequency generated by crystal oscillator
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization from Assumes full supply voltage reached within
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
14.318
Max.
2
2
55
3
25
Unit
V/ns
V/ns
%
ms
Ω
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Note:
9. PCI clock is CPU/4 for CPU = 133 MHz and CPU/3 for CPU = 100 MHz.
Min.
0.5
0.5
45
Typ.
48.008
+167
57/17
25
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
Ω
6