W161 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 133-MHz Spread Spectrum FTG for Pentium II Platforms

PRELIMINARY
W161
133-MHz Spread Spectrum FTG for Pentium® II Platforms
Features
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• Three copies of CPU outputs at 100 or 133 MHz
• Three copies of 66-MHz output at 3.3V
• Ten copies of PCI clocks at 33 MHz, 3.3V
• Two copies of 14.318-MHz reference output at 3.3V
• One copy of 48-MHz USB clock
• One copy of CPU-divide-by-2 output as reference input
to Direct Rambus™ Clock Generator (Cypress W134)
• Available in 48-pin SSOP (300 mils)
Key Specifications
Supply Voltages: ...................................... V_DDQ2 = 2.5V±5%
V_DDQ3 = 3.3V±5%
CPU, CPUdiv2 Output Jitter:....................................... 250 ps
CPU, CPUdiv2 Output Skew: ...................................... 175 ps
IOAPIC, 3V66 Output Skew: ....................................... 250 ps
PCI0:9 Output Skew: .................................................. 500 ps
Duty Cycle: ................................................................... 45/55
Block Diagram
X1
XTAL
X2
OSC
2
REF_[0:1]
3
CPU_[0:2]
SPREAD#
SEL0
SEL1
SEL133/100#
PLL 1
÷2
÷2/÷1.5
CPUdiv2
3
3V66_[0:2]
PWRDWN#
÷2
Power
Down
÷2
Logic
Three-state
Logic
9
PCI_[0:9]
IOAPIC
Spread Spectrum Modulation:..................................... –0.5%
CPU to 3V66 Output Offset: ............. 0.0–1.5 ns (CPU leads)
3V66 to PCI Output Offset:.............. 1.5–3.0 ns (3V66 leads)
CPU to IOAPIC Output Offset: ......... 1.5–4.0 ns (CPU leads)
Table 1. Pin Selectable Frequency
SEL133/100# SEL1 SEL0
Function
0
0
0 All outputs Three-State
0
0
1 (Reserved)
0
1
0 Active 100-MHz, 48-MHz
PLL inactive
0
1
1 Active 100-MHz, 48-MHz
PLL active
1
0
0 Test Mode
1
0
1 (Reserved)
1
1
0 Active 133-MHz, 48-MHz
PLL inactive
1
1
1 Active 133-MHz, 48-MHz
PLL active
Pin Configuration^[1]
REF0 1
REF1 2
VDDQ3 3
X1 4
X2 5
GND 6
PCI0 7
PCI1 8
VDDQ3 9
PCI2 10
PCI3 11
PCI4 12
PCI5 13
GND 14
PCI6 15
PCI7 16
VDDQ3 17
PCI8 18
PCI9 19
GND 20
3V66_0 21
3V66_1 22
3V66_2 23
VDDQ3 24
48 GND
47 VDDQ2
46 IOAPIC
45 GND
44 VDDQ2
43 CPUdiv2
42 GND
41 VDDQ2
40 CPU2
39 GND
38 VDDQ2
37 CPU1
36 CPU0
35 GND
34 VDDQ3
33 GND
32 PWRDWN#*
31 SPREAD#*
30 SEL1*
29 SEL0*
28 VDDQ3
27 48MHz
26 GND
25 SEL133/100#
Note:
1. Internal 250-kΩ pull-up resistors present on inputs marked with *.
Design should not rely solely on internal pull-up resistor to set I/O
pins HIGH.
PLL2
48MHz
Pentium is a registered trademark of Intel Corporation. Direct Rambus is a trademark of Rambus, Inc.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 13, 1999, rev. **