CY7C1440AV25 Datasheet, PDF (6/32 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Pin Configurations (continued)
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1442AV25 (512K x 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQ_{G DQG}
A
CE₂ ADSP ADSC
ADV CE₃
A
DQ_{B DQB}
B
DQ_G DQ_{G BWSC BWSG NC/288M BW}
A
BWS_{B BWSF} DQ_{B DQB}
C
DQ_{G DQG BWSH BWSD NC/144M CE1 NC/576M BWSE BWSA DQB DQB}
D
DQ_G DQ_G V_SS
NC ^{NC/1G OE}
GW NC
V_SS
DQ_B DQ_B
E
DQP_G DQP_C V_DDQ V_{DDQ VDD}
V_DD
V_DD
V_DDQ V_{DDQ DQPF DQPB}
F
DQ_{C DQC VSS}
V_SS
V_SS NC
V_{SS VSS}
V_SS
DQ_{F DQF}
G
DQ_C DQ_C V_DDQ V_{DDQ VDD NC}
V_DD
V_DDQ V_{DDQ DQF}
DQ_F
H
DQ_{C DQC VSS}
V_SS
V_{SS NC}
V_SS V_SS
V_SS
DQ_{F DQF}
J
DQ_C DQ_C V_DDQ V_DDQ V_{DD NC}
V_DD
V_DDQ V_{DDQ DQF}
DQ_F
K
NC
NC CLK _NC
V_SS V_SS
V_SS
NC
NC NC
NC
L
DQ_H DQ_H V_DDQ V_DDQ V_DD NC
V_DD
V_DDQ
V_DDQ
DQ_A
DQ_A
M
DQ_{H DQH} V_SS
V_SS
V_SS NC
V_SS V_SS
V_SS
DQ_{A DQA}
N
DQ_H DQ_H V_DDQ V_DDQ V_DD NC
V_DD V_DDQ V_{DDQ DQA DQA}
P
DQ_H DQ_H V_SS
V_SS
V_{SS ZZ}
V_SS V_SS
V_SS
DQ_A DQ_A
R
DQP_D DQP_H V_DDQ V_DDQ V_DD V_DD
V_DD
V_DDQ
V_{DDQ DQPA DQPE}
T
DQ_D DQ_D V_SS
NC
NC _MODE NC
NC
V_SS
DQ_E DQ_E
U
DQ_D DQ_D NC/72M ^A
A
V
DQ_D DQ_D A
A
A
W
DQ_D DQ_{D TMS}
TDI
A
A
A
A1
A
A0
A
A
A
DQ_E DQ_E
A
A
DQ_E DQ_E
TDO
TCK
DQ_E DQ_E
Pin Definitions
Name
A₀, A₁, A
BW_A, BW_B, BW_C,
BW_D, BW_E, BW_F,
BW_G, BW_H
GW
BWE
CLK
CE₁
I/O
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE₁, CE₂, and CE₃ ^[2]are sampled
active. A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW_X
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE₂ and CE₃ to select/deselect the device. ADSP is ignored if CE₁ is
HIGH. CE₁ is sampled only when a new external address is loaded.
Document #: 38-05350 Rev. *E
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