CY7C1440AV25 Datasheet, PDF (19/32 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V_DD Relative to GND........ –0.3V to +3.6V
Supply Voltage on V_DDQ Relative to GND ...... –0.3V to +V_DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V_DDQ + 0.5V
DC Input Voltage ................................... –0.5V to V_DD + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V_DD
2.5V + 5%
Industrial –40°C to +85°C
V_DDQ
1.7V to V_DD
Electrical Characteristics Over the Operating Range ^{[16, 17]}
DC Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
V_DD
V_DDQ
Power Supply Voltage
I/O Supply Voltage
for 2.5V I/O
for 1.8V I/O
2.375
2.375
1.7
V_OH
Output HIGH Voltage for 2.5V I/O, I_OH = –1.0 mA
for 1.8V I/O, I_OH = –100 µA
V_OL
Output LOW Voltage for 2.5V I/O, I_OL = 1.0 mA
for 1.8V I/O, I_OL= 100 µA
V_IH
Input HIGH Voltage^[16] for 2.5V I/O
for 1.8V I/O
V_IL
Input LOW Voltage^[16] for 2.5V I/O
for 1.8V I/O
I_X
Input Leakage Current GND ≤ V_I ≤ V_DDQ
except ZZ and MODE
2.0
1.6
1.7
1.26
–0.3
–0.3
–5
Input Current of MODE Input = V_SS
–30
Input = V_DD
Input Current of ZZ
Input = V_SS
–5
Input = V_DD
I_OZ
Output Leakage Current GND ≤ V_I ≤ V_DDQ, Output Disabled
–5
I_DD
V_DD Operating Supply V_DD = Max., I_OUT = 0 mA,
4-ns cycle, 250 MHz
Current
f = f_MAX = 1/t_CYC
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
I_SB1
Automatic CE
V_DD = Max, Device Deselected, All speeds
Power-down
V_IN ≥ V_IH or V_IN ≤ V_IL
Current—TTL Inputs f = f_MAX = 1/t_CYC
I_SB2
Automatic CE
V_DD = Max, Device Deselected, All speeds
Power-down
V_IN ≤ 0.3V or V_IN > V_DDQ – 0.3V,
Current—CMOS Inputs f = 0
I_SB3
Automatic CE
V_DD = Max, Device Deselected, or All speeds
Power-down
V_IN ≤ 0.3V or V_IN > V_DDQ – 0.3V
Current—CMOS Inputs f = f_MAX = 1/t_CYC
I_SB4
Automatic CE
V_DD = Max, Device Deselected, All speeds
Power-down
V_IN ≥ V_IH or V_IN ≤ V_IL, f = 0
Current—TTL Inputs
Notes:
16. Overshoot: V_IH(AC) < V_DD +1.5V (Pulse width less than t_CYC/2), undershoot: V_IL(AC) > –2V (Pulse width less than t_CYC/2).
17. TPower-up: Assumes a linear ramp from 0V to V_DD(min.) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
Max. Unit
2.625
V
2.625
V
1.9
V
V
V
0.4
V
0.2
V
V_DD + 0.3V V
V_DD + 0.3V V
0.7
V
0.36
V
5
µA
µA
5
µA
µA
30
µA
5
µA
435
mA
385
mA
335
mA
185
mA
120
mA
160
mA
135
mA
Document #: 38-05350 Rev. *E
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