CY7C1440AV25 Datasheet, PDF (2/32 Pages) Cypress Semiconductor – 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM

CY7C1440AV25
CY7C1442AV25
CY7C1446AV25
Logic Block Diagram – CY7C1440AV25 (1M x 36)
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWD
BWC
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2
A[1:0]
Q1
BURST
COUNTER
CLR AND Q0
LOGIC
DQD ,DQPD
BYTE
WRITE REGISTER
DQC ,DQPC
BYTE
WRITE REGISTER
DQB ,DQPB
BYTE
WRITE REGISTER
DQA ,DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQD ,DQPD
BYTE
WRITE DRIVER
DQC ,DQPC
BYTE
WRITE DRIVER
DQB ,DQPB
BYTE
WRITE DRIVER
DQA ,DQPA
BYTE
WRITE DRIVER
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1442AV25 (2M x 18)
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BWB
BWA
BWE
GW
CE1
CE2
CE3
OE
ADDRESS
REGISTER
2 ^A[1:0]
BURST ^Q1
COUNTER AND
LOGIC
CLR
Q0
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQB,DQPB
WRITE DRIVER
DQA,DQPA
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
DQPC
DQPD
INPUT
REGISTERS
MEMORY
ARRAY
SENSE
OUTPUT
AMPS
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQPA
DQPB
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document #: 38-05350 Rev. *E
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