CY14B101P Datasheet, PDF (6/33 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock

PRELIMINARY
CY14B101P
Figure 3. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14B101P
CS
HOLD
SCK SI
SO
CY14B101P
CS
HOLD
SPI Modes
CY14B101P device may be driven by a microcontroller with its
SPI peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL=0, CPHA=0)
■ SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, input data is latched in on the rising edge
of Serial Clock (SCK) starting from the first rising edge after CS
goes active. If the clock starts from a HIGH state (in mode 3), the
first rising edge after the clock toggles are considered. The
output data is available on the falling edge of Serial Clock (SCK).
Figure 4. SPI Mode 0
CS
SCK
012 345 67
The two SPI modes are shown in Figure 4 and Figure 5. The
status of clock when the bus master is in Standby mode and not
transferring data is:
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. CY14B101P detects the SPI mode
from the status of SCK pin when device is selected by bringing
the CS pin LOW. If SCK pin is LOW when device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, CY14B101P works
in SPI Mode 3.
Figure 5. SPI Mode 3
CS
SCK
012 34567
SI
7 654321 0
MSB
LSB
SI
7 654321 0
MSB
LSB
Document #: 001-44109 Rev. *C
Page 6 of 33
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