CY14B101P Datasheet, PDF (1/33 Pages) Cypress Semiconductor – 1 Mbit (128K x 8) Serial SPI nvSRAM with Real Time Clock

PRELIMINARY
CY14B101P
1 Mbit (128K x 8) Serial SPI nvSRAM
with Real Time Clock
Features
■ 1 Mbit Nonvolatile SRAM
❐ Internally organized as 128K x 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power down (AutoStore) or by user using
HSB pin (Hardware Store) or SPI instruction (Software Store)
❐ RECALL to SRAM initiated on power up (Power Up Recall)
or by SPI Instruction (Software Recall)
❐ Automatic STORE on power down with a small capacitor
■ High Reliability
❐ Infinite Read, Write, and RECALL cycles
❐ 200,000 STORE cycles to QuantumTrap
❐ Data Retention: 20 Years
■ Real Time Clock
❐ Full featured Real Time Clock
❐ Watchdog timer
❐ Clock alarm with programmable interrupts
❐ Capacitor or battery backup for RTC
❐ Backup current of 300 nA
■ High Speed Serial Peripheral Interface (SPI)
❐ 40 MHz Clock rate - SRAM Memory access
❐ 25 MHz Clock rate - RTC Memory access
❐ Supports SPI Modes 0 (0,0) and 3 (1,1)
■ Write Protection
❐ Hardware Protection using Write Protect (WP) Pin
❐ Software Protection using Write Disable Instruction
❐ Software Block Protection for 1/4, 1/2, or entire Array
■ Low Power Consumption
❐ Single 3V +20%, –10% operation
❐ Average V_CC current of 10 mA at 40 MHz operation
■ Industry Standard Configurations
❐ Commercial and industrial temperatures
❐ 16-pin SOIC Package
❐ RoHS compliant
Overview
The Cypress CY14B101P combines a 1 Mbit nonvolatile static
RAM with full featured real time clock in a monolithic integrated
circuit with serial SPI interface. The memory is organized as
128K words of 8 bits each. The embedded nonvolatile elements
incorporate the QuantumTrap technology, creating the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while the QuantumTrap cells provide
highly reliable nonvolatile storage of data. Data transfers from
SRAM to the nonvolatile elements (STORE operation) takes
place automatically at power down. On power up, data is
restored to the SRAM from the nonvolatile memory (RECALL
operation). The STORE and RECALL operations can also be
initiated by the user.
Logic Block Diagram
V_CC
V_CAP
CS
WP
SCK
HOLD
SI
Instruction decode
Write protect
Control logic
Quantum Trap
128K X 8
SRAM ARRAY
128K X 8
STORE
RECALL
Power Control
STORE/RECALL
Control
Instruction
register
Address
Decoder
A0-A16
D0-D7
Data I/O register
RTC
MUX
Status register
HSB
Xout
Xin
INT
SO
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-44109 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 02, 2009
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