CYRF69103_08 Datasheet, PDF (59/65 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

90%
Figure 20. GPIO Timing Diagram
CYRF69103
GPIO Pin Output
Voltage
10%
T_{R_GPIO}
T_{F_GPIO}
Figure 21. SPI Master Timing, CPHA = 1
SS
(SS is under firmware control in SPI Master mode)
SCK (CPOL=0)
T_SCKH
T_SCKL
SCK (CPOL=1)
T_MDO
MOSI
MSB
LSB
MISO
MSB
LSB
T_MSU T_MHD
Document #: 001-07611 Rev *C
Page 59 of 65
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