CYRF69103_10 Datasheet, PDF (57/68 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
22. Radio Function Register Summary
Address
0x00
0x01
Mnemonic
CHANNEL_ADR
TX_LENGTH_ADR
0x02
TX_CTRL_ADR
0x03
TX_CFG_ADR
0x04
TX_IRQ_STATUS_ADR
0x05
0x06
RX_CTRL_ADR
RX_CFG_ADR
0x07
0x08
0x09
0x0A
0x0B
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x26
XTAL_CTRL_ADR
IO_CFG_ADR
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
EOP_CTRL_ADR ^[9.]
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
RX_OVERRIDE_ADR
TX_OVERRIDE_ADR
XTAL_CFG_ADR
b7
b6
Not Used
TX GO
Not Used
OS
IRQ
RX GO
AGC EN
RXOW
IRQ
RX ACK
TX CLR
Not Used
LV
IRQ
RSVD
LNA
SOPDET
IRQ
PKT ERR
PMU EN
LVIRQ EN
XOUT FN
IRQ OD
IRQ POL
XOUT OP MISO OP
ACK EN
Not Used
SOP EN
SOP LEN
Not Used
Not Used
Not Used
Not Used
SOP
Not Used
HEN
Not Used
RSVD
ACK RX
ACK TX
RSVD
Not Used
RSVD
RXTX DLY
FRC PRE
RSVD
b5
TXB15
IRQEN
DATA CODE
LENGTH
TXB15
IRQ
RXB16
IRQEN
ATT
RXB16
IRQ
EOP ERR
PMU Mode
Force
b4
b3
Channel
TX Length
TXB8
IRQEN
TXB0
IRQEN
b2
TXBERR
IRQEN
DATA MODE
TXB8
IRQ
TXB0
IRQ
TXBERR
IRQ
RXB8
IRQEN
RXB1
IRQEN
RXBERR
IRQEN
FAST TURN
HILO
EN
Not Used
RXB8
IRQ
RXB1
IRQ
RXBERR
IRQ
CRC0 Bad CRC RX Code
RX Count
RX Length
PFET
disable
[10.]
LVI TH
b1
b0
TXC
IRQEN
TXE
IRQEN
PA SETTING
TXC
IRQ
RXC
IRQEN
TXE
IRQ
RXE
IRQEN
RXOW EN
VLD EN
RXC
IRQ
RXE
IRQ
RX Data Mode
PMU OUTV
XSIRQ EN
MISO OD
PACTL OP
FRC END
LEN EN
Not Used
Not Used
LNA
HINT
Not Used
FRC SEN
MAN RXACK
RSVD
RSVD
Not Used Not Used
FREQ
XOUT OD PACTL OD PACTL GPIO SPI 3PIN
IRQ GPIO
IRQ OP XOUT IP MISO IP
PACTL IP
IRQ IP
END STATE
ACK TO
SOP TH
Not Used
TH32
TH64
RSSI
EOP
CRC SEED LSB
CRC SEED MSB
CRC LSB
CRC MSB
CRC LSB
CRC MSB
STRIM LSB
Not Used
STRIM MSB
FRC AWAKE
Not Used
Not Used
RST
FRC
RXDR
DIS CRC0 DIS RXCRC
ACE
Not Used
MAN
TXACK OVRD ACK DIS TXCRC
RSVD
TX INV
RSVD START DLY RSVD
RSVD
RSVD
0x27
CLK_OVERRIDE_ADR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
0x28
CLK_EN_ADR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
0x29
RX_ABORT_ADR
RSVD
RSVD
ABORT EN RSVD
RSVD
RSVD
RSVD
RSVD
0x32
AUTO_CAL_TIME_ADR
AUTO_CAL_TIME
0x35
AUTO_CAL_OFFSET_ADR
AUTO_CAL_OFFSET
0x39
ANALOG_CTRL_ADR
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RX INV
ALL SLOW
Register Files
0x20
TX_BUFFER_ADR
TX Buffer File
0x21
0x22
0x23
0x24
0x25
RX_BUFFER_ADR
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
RX Buffer File
SOP Code File
Data Code File
Preamble File
MFG ID File
Default^[4]
-1001000
00000000
00000011
Access^[4]
-bbbbbbb
bbbbbbbb
bbbbbbbb
--000101 --bbbbbb
--------
rrrrrrrr
00000111 bbbbbbbb
10010-10 bbbbb-bb
--------
brrrrrrr
--------
00000000
00000000
10100000
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbb-bbbb
000--100
00000000
0000----
1-000000
10100101
----0100
---01010
0-100000
10100100
00000000
00000000
--------
--------
11111111
11111111
00000000
----0000
00000--0
0000000-
bbb--bbb
bbbbbbbb
bbbbrrrr
b-bbbbbb
bbbbbbbb
----bbbb
---bbbbb
r-rrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbbbbbbb
----bbbb
wwwww--w
bbbbbbb-
00000000 bbbbbbbb
00000000
00000000
00000000
00000000
00000011
00000000
00000000
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
wwwwwww
w
--------
--------
Note [5]
Note [6]
Note [7]
NA
wwwwwww
w
rrrrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
All registers are read and writable, except where noted. Registers may be written to or read from either individually or in sequential
groups. A single-byte read or write reads or writes from the addressed register. Incrementing burst read and write is a sequence that
begins with an address, and then reads or writes to/from each register in address order for as long as clocking continues. It is possible
to repeatedly read (poll) a single register using a nonincrementing burst read.
Notes
4. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.
5. SOP_CODE_ADR default = 0x17FF9E213690C782.
6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
7. PREAMBLE_ADR default = 0x333302;The count value must be great than 4 for DDR and greater than 8 for SDR
8. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode.The PMU, GPIOs, RSSI registers can be accessed in Active Tx and Rx mode.
9. EOP_CTRL_ADR[6:4] must never have the value of “000” i.e. EOP Hint Symbol count must never be “0”
10. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.om Vcc when the
PMU is disabled to the radio.
Document #: 001-07611 Rev *F
Page 57 of 68
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