CYRF69103_10 Datasheet, PDF (31/68 Pages) Cypress Semiconductor – Programmable Radio on Chip Low Power

CYRF69103
16. Reset
The microcontroller supports two types of resets: Power on Reset (POR) and Watchdog Reset (WDR). When reset is initiated, all
registers are restored to their default states and all interrupts are disabled.
The occurrence of a reset is recorded in the System Status and Control Register (CPU_SCR). Bits within this register record the
occurrence of POR and WDR Reset respectively. The firmware can interrogate these bits to determine the cause of a reset.
The microcontroller resumes execution from Flash address 0x0000 after a reset. The internal clocking mode is active after a reset,
until changed by user firmware.
Note The CPU clock defaults to 3 MHz (Internal 24 MHz Oscillator divide-by-8 mode) at POR to guarantee operation at the low V_CC
that might be present during the supply ramp.
Table 16-1. System Status and Control Register (CPU_SCR) [0xFF] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
GIES
R
Reserved
–
WDRS
R/C^[3]
PORS
R/C^[3]
Sleep
R/W
Reserved
–
Reserved
–
Stop
R/W
Default
0
0
0
1
0
1
0
0
The bits of the CPU_SCR register are used to convey status and control of events for various functions of a CYRF69103
device.
Bit 7
GIES
The Global Interrupt Enable Status bit is a read-only status bit and its use is discouraged. The GIES bit is a legacy
bit, which was used to provide the ability to read the GIE bit of the CPU_F register. However, the CPU_F register
is now readable. When this bit is set, it indicates that the GIE bit in the CPU_F register is also set which, in turn,
indicates that the microprocessor services interrupts:
0 = Global interrupts disabled
1 = Global interrupt enabled
Bit 6
Reserved
Bit 5
WDRS
The WDRS bit is set by the CPU to indicate that a WDR event has occurred. The user can read this bit to
determine the type of reset that has occurred. The user can clear but not set this bit:
0 = No WDR
1 = A WDR event has occurred
Bit 4
PORS
The PORS bit is set by the CPU to indicate that a POR event has occurred. The user can read this bit to deter-
mine the type of reset that has occurred. The user can clear but not set this bit:
0 = No POR
1 = A POR event has occurred (Note that WDR events do not occur until this bit is cleared).
Bit 3
SLEEP
Set by the user to enable CPU sleep state. CPU remains in sleep mode until any interrupt is pending. The Sleep
bit is covered in more detail in the section Sleep Mode on page 32.
0 = Normal operation
1 = Sleep
Bits 2:1 Reserved
Bit 0
STOP
This bit is set by the user to halt the CPU. The CPU remains halted until a reset (WDR, POR, or external reset)
has taken place. If an application wants to stop code execution until a reset, the preferred method is to use the
HALT instruction rather than writing to this bit.
0 = Normal CPU operation
1 = CPU is halted (not recommended)
Note
3. C = Clear. This bit can only be cleared by the user and cannot be set by firmware.
Document #: 001-07611 Rev *F
Page 31 of 68
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