CY8C54_11 Datasheet, PDF (54/105 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C54 Family Datasheet
8.11.1 Down Mixer
The S+H can be used as a mixer to down convert an input signal.
This circuit is a high bandwidth passive sample network that can
sample input signals up to 14 MHz. This sampled value is then
held using the opamp with a maximum clock rate of 4 MHz. The
output frequency is at the difference between the input frequency
and the highest integer multiple of the Local Oscillator that is less
than the input.
8.11.2 First Order Modulator - SC Mode
A first order modulator is constructed by placing the switched
capacitor block in an integrator mode and using a comparator to
provide a 1-bit feedback to the input. Depending on this bit, a
reference voltage is either subtracted or added to the input
signal. The block output is the output of the comparator and not
the integrator in the modulator case. The signal is downshifted
and buffered and then processed by a decimator to make a
delta-sigma converter or a counter to make an incremental
converter. The accuracy of the sampled data from the first-order
modulator is determined from several factors.
The main application for this modulator is for a low frequency
ADC with high accuracy. Applications include strain gauges,
thermocouples, precision voltage, and current measurement
9. Programming, Debug Interfaces,
Resources
The Cortex-M3 has internal debugging components, tightly
integrated with the CPU, providing the following features:
„ JTAG or SWD access
„ Flash Patch and Breakpoint (FPB) block for implementing
breakpoints and code patches
„ Data Watchpoint and Trigger (DWT) block for implementing
watchpoints, trigger resources, and system profiling
„ Embedded Trace Macrocell (ETM) for instruction trace
„ Instrumentation Trace Macrocell (ITM) for support of printf-style
debugging
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
JTAG and SWD support all programming and debug features of
the device. The SWV and TRACEPORT provide trace output
from the DWT, ETM, and ITM. TRACEPORT is faster but uses
more pins. SWV is slower but uses only one pin.
Cortex-M3 debug and trace functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC interfaces are fully compatible
with industry standard third party tools.
All Cortex-M3 debug and trace modules are disabled by default
and can only be enabled in firmware. If not enabled, the only way
to reenable them is to erase the entire device, clear flash
protection, and reprogram the device with new firmware that
enables them. Disabling debug and trace features, robust flash
protection, and hiding custom analog and digital functionality
inside the PSoC device provide a level of security not possible
with multichip application solutions. Additionally, all device
interfaces can be permanently disabled (Device Security) for
applications concerned about phishing attacks due to a
maliciously reprogrammed device. Permanently disabling
interfaces is not recommended in most applications because the
designer then cannot access the device. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
9.1 SWD Interface
SWD is the default debug interface and is always enabled after
any reset, including POR. This means that the two pins used for
SWD (P1.0 and P1.1) should not generally be used for any other
purpose since they always revert to being SWD pins after any
reset.
The SWD interface is the preferred alternative to JTAG, as it
requires only two pins. The SWD clock frequency can be up to
1/3 of the CPU clock frequency.
SWD uses two pins, either two port 1 pins or the USBIO D+ and
D- pins. The SWD pins cannot be used as GPIO. The USBIO
pins are useful for in system programming of USB solutions that
would otherwise require a separate programming connector.
One pin is used for the data clock and the other is used for data
input and output. SWD can be enabled on only one of the pin
pairs at a time. SWD is used for debugging or for programming
the flash memory. In addition, the SWD interface supports the
SWV trace output if desired.
9.2 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four pins.
The JTAG clock frequency can be up to 8 MHz, or 1/3 of the CPU
clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU clock
frequency for 32-bit transfers, whichever is least. The JTAG
interface is used for programming the flash memory and
debugging.
Note that, while the debug interface at reset is always SWD, any
standard SWD or JTAG debugging tool can switch from SWD to
4-pin JTAG or vice versa without requiring port acquisition, using
a standard sequence defined by ARM.
When using JTAG pins as standard GPIO, make sure that the
GPIO functionality and PCB circuits do not interfere with JTAG
use.
Document Number: 001-66238 Rev. **
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