CY8C54_11 Datasheet, PDF (28/105 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC®)

PRELIMINARY
PSoC^® 5: CY8C54 Family Datasheet
Figure 6-9. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
Buffer
Thresholds
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Interrupt
Logic
Input Buffer Disable
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
0
Digital System Output
1
In
PRT[x]BYP
Driver
Vhigh
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Drive
Logic
Slew
Cntl
Bidirectional Control
PRT[x]BIE
OE
PIN
Figure 6-10. USBIO Block Diagram
Digital Input Path
USB Receiver Circuitry
PRT[x]DBL_SYNC_IN
USBIO_CR1[0,1]
Digital System Input
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PICU[x]INTTYPE[y]
PICU[x]INTSTAT
Pin Interrupt Signal
PICU[x]INTSTAT
Interrupt
Logic
Digital Output Path
PRT[x]SYNC_OUT
USBIO_CR1[7]
USB SIE Control for USB Mode
USBIO_CR1[4,5]
0
Digital System Output
1
PRT[x]BYP
USBIO_CR1[2]
USBIO_CR1[3]
USBIO_CR1[6]
USB or I/O
In
Drive
Logic
D+ pin only
Vddd Vddd Vddd
Vddd
5 k 1.5 k
D+ 1.5 k
D+D- 5 k
Open Drain
PIN
Document Number: 001-66238 Rev. **
Page 28 of 105
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