BCM20730 Datasheet, PDF (52/62 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver for Wireless Input Devices

BCM20730 Data Sheet
Timing and AC Characteristics
Table 22: SPI2 Timing Values — SCLK = 6 MHz and VDDM = 1.62V^a
Reference Characteristics
Symbol Min
Typical^b Max Unit
1
Output setup time, from MOSI
Tds_mo –
data valid to sample edge of SCLK
50
–
ns
2
Output hold time, from sample Tdh_mo –
edge of SCLK to MOSI data update
120
–
ns
3
Input setup time, from MISO
Tds_mi –
data valid to sample edge of SCLK
4
Input hold time, from sample
Tdh_mi –
edge of SCLK to MISO data update
TBD
–
ns
TBD
–
ns
5^c
Time from CS assert to first SCLK Tsu_cs ½ SCLK period – 1 –
edge
6^c
Time from first SCLK edge to CS Thd_cs ½ SCLK period
–
deassert
–
ns
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
BSC Interface Timing
Table 23: BSC Interface Timing Specifications
Reference
Characteristics
Min Max Unit
1
Clock frequency
–
100 kHz
2
START condition setup time
400
800
1000
650 –
ns
3
START condition hold time
4
Clock low time
5
Clock high time
6
Data input hold time^a
7
Data input setup time
8
STOP condition setup time
9
Output valid from clock
10
Bus free time^b
280 –
ns
650 –
ns
280 –
ns
0
–
ns
100 –
ns
280 –
ns
–
400 ns
650 –
ns
a. As a transmitter, 300 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid
unintended generation of START or STOP conditions.
b. Time that the cbus must be free before a new transaction can start.
BROADCOM ®
September 9, 2013 • 20730-DS108-R
BROADCOM CONFIDENTIAL
Page 51