BCM20730 Datasheet, PDF (50/62 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver for Wireless Input Devices

BCM20730 Data Sheet
Timing and AC Characteristics
SPI Timing
The SPI interface supports clock speeds up to 12 MHz with VDDIO ≥ 2.2V. The supported clock speed is 6 MHz
when 2.2V ≥ VDDIO ≥ 1.62V.
Figure 13 shows the timing diagram. SPI timing values for different values of SCLK and VDDM are shown in
Table 19, Table 20 on page 50, Table 21 on page 50, Table 22 on page 51.
Figure 13: SPI Timing Diagram
5
6
CS
SCLK
Mode 1
SCLK
Mode 3
2
1
MOSI
MSB
LSB
4
3
MISO
Invalid bit
MSB
LSB
Table 19: SPI1 Timing Values — SCLK = 12 MHz and VDDM = 3.2V^a
Reference Characteristics
Symbol Min
Typical^b Max Unit
1
Output setup time, from MOSI
Tds_mo –
data valid to sample edge of SCLK
2
Output hold time, from sample Tdh_mo –
edge of SCLK to MOSI data update
3
Input setup time, from MISO data Tds_mi –
valid to sample edge of SCLK
20
–
ns
63
–
ns
TBD
–
ns
4
Input hold time, from sample
Tdh_mi –
edge of SCLK to MISO data update
TBD
–
ns
5^c
Time from CS assert to first SCLK Tsu_cs ½ SCLK period – 1 –
edge
–
ns
6^c
Time from first SCLK edge to CS Thd_cs ½ SCLK period
–
deassert
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled.
BROADCOM ®
September 9, 2013 • 20730-DS108-R
BROADCOM CONFIDENTIAL
Page 49