BCM20730 Datasheet, PDF (51/62 Pages) Cypress Semiconductor – Single-Chip Bluetooth Transceiver for Wireless Input Devices

BCM20730 Data Sheet
Timing and AC Characteristics
Table 20: SPI1 Timing Values—SCLK = 6 MHz and VDDM = 1.62V^a
Reference Characteristics
Symbol Min
Typical^b Max Unit
1
Output setup time, from MOSI data Tds_mo –
valid to sample edge of SCLK
41
–
ns
2
Output hold time, from sample Tdh_mo –
edge of SCLK to MOSI data update
120
–
ns
3
Input setup time, from MISO
Tds_mi –
data valid to sample edge of SCLK
4
Input hold time, from sample
Tdh_mi –
edge of SCLK to MISO data update
TBD
–
ns
TBD
–
ns
5^c
Time from CS assert to first SCLK Tsu_cs ½ SCLK period – 1 –
edge
6^c
Time from first SCLK edge to CS Thd_cs ½ SCLK period
–
deassert
–
ns
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 6 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF/1 MΩ load and SCLK = 6 MHz.
c. CS timing is firmware controlled.
Table 21: SPI2 Timing Values — SCLK = 12 MHz and VDDM = 3.2V^a
Reference Characteristics
Symbol Min
Typical^b Max Unit
1
Output setup time, from MOSI
Tds_mo –
data valid to sample edge of SCLK
2
Output hold time, from sample Tdh_mo –
edge of SCLK to MOSI data update
26
–
ns
56
–
ns
3
Input setup time, from MISO
Tds_mi –
data valid to sample edge of SCLK
TBD
–
ns
4
Input hold time, from sample
Tdh_mi –
edge of SCLK to MISO data update
TBD
–
ns
5^c
Time from CS assert to first SCLK Tsu_cs ½ SCLK period – 1 –
edge
–
ns
6^c
Time from first SCLK edge to CS Thd_cs ½ SCLK period
–
deassert
–
ns
a. The SCLK period is based on the limitation of Tds_mi. SCLK is designed for a maximum speed of 12 MHz. The
speed can be adjusted to as low as 400 Hz by configuring the firmware.
b. Typical timing based on 20 pF//1 MΩ load and SCLK = 12 MHz.
c. CS timing is firmware controlled in master mode and can be adjusted as required in slave mode.
BROADCOM ®
September 9, 2013 • 20730-DS108-R
BROADCOM CONFIDENTIAL
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