CYBL1XX7X Datasheet, PDF (5/42 Pages) Cypress Semiconductor – Programmable Radio-on-Chip With Bluetooth Low Energy (PRoC™ BLE)

PRELIMINARY
PRoC™ BLE: CYBL1XX7X
Family Datasheet
CPU Subsystem
CPU
The CYBL1XX7X device is based on an energy-efficient
ARM Cortex-M0 32-bit processor, offering low power
consumption, high performance, and reduced code size using
16-bit thumb instructions. The Cortex-M0’s ability to perform
single-cycle 32-bit arithmetic and logic operations, including
single-cycle 32-bit multiplication, helps in better performance.
The inclusion of the tightly-integrated Nested Vectored Interrupt
Controller (NVIC) with 32 interrupt lines enables the Cortex-M0
to achieve a low latency and a deterministic interrupt response.
The CPU also includes a 2-pin interface, the serial wire debug
(SWD), which is a 2-wire form of JTAG. The debug circuits are
enabled by default and can only be disabled in firmware. If
disabled, the only way to re-enable them is to erase the entire
device, clear flash protection, and reprogram the device with the
new firmware that enables debugging. In addition, it is possible
to use the debug pins as GPIO too. The device has four break-
points and two watchpoints for effective debugging.
Flash
The device has a 256-KB flash memory with a flash accelerator,
tightly coupled to the CPU to improve average access times from
flash. The flash is designed to deliver 1-wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average. Part of the flash can be used to
emulate EEPROM operation, if required.
During flash erase and programming operations (the maximum
erase and program time is 20 ms per row), the IMO will be set to
48 MHz for the duration of the operation. This also applies to the
emulated EEPROM. System design must take this into account
because peripherals operating from different IMO frequencies
will be affected. If it is critical that peripherals continue to operate
with no change during flash programming, always set the IMO to
48 MHz and derive the peripheral clocks by dividing down from
this frequency.
SRAM
The low-power 32-KB SRAM memory retains its contents even
in Hibernate mode.
ROM
The 8-KB supervisory ROM contains a library of executable
functions for flash programming. These functions are accessed
through supervisory calls (SVC) and enable in-system
programming of the flash memory.
DMA
DMA controller provides DataWrite (DW) and Direct Memory
Access (DMA). The DMA controller has following features
■ Supports up to 8 DMA channels with two independent
descriptors per channel
■ Four levels of priority for each channel
■ Byte, half-word (2 bytes), and word (4 bytes) transfers
■ Three modes of operation supported for each channel
■ Configurable interrupt generation
■ Output trigger on completion of transfer (transfer sizes up to
65536 data elements)
BLE Subsystem
The BLE subsystem consists of the link layer engine and
physical layer. The link layer engine supports both master and
slave roles. The link layer engine implements time-critical
functions such as encryption in the hardware to reduce the
power consumption, and provides minimal processor
intervention and a high performance. The key protocol elements,
such as host control interface (HCI) and link control, are
implemented in firmware. The direct test mode (DTM) is included
to test the radio performance using a standard Bluetooth tester.
The physical layer consists of a modem and an RF transceiver
that transmits and receives BLE packets at the rate of 1 Mbps
over the 2.4-GHz ISM band. In the transmit direction, this block
performs GFSK modulation and then converts the digital
baseband signal of these BLE packets into radio frequency
before transmitting them to air through an antenna. In the receive
direction, this block converts an RF signal from the antenna to a
digital bit stream after performing GFSK demodulation.
The RF transceiver contains an integrated balun, which provides
a single-ended RF port pin to drive a 50-Ω antenna terminal
through a pi-matching network. The output power is
programmable from –18 dBm to +3 dBm to optimize the current
consumption for different applications.
The Bluetooth Low Energy protocol stack uses the BLE
subsystem and provides the following features:
■ Link Layer (LL)
❐ Master and Slave roles
❐ 128-bit AES engine
❐ Encryption
❐ Low-duty-cycle advertising
❐ LE Ping
❐ LE Data Packet Length Extension (Bluetooth 4.2 feature)
❐ Link Layer Privacy (with extended scanning filter policy)
(Bluetooth 4.2 feature)
■ Bluetooth Low Energy 4.2 single-mode protocol stack with
logical link control and adaptation protocol (L2CAP), attribute
(ATT), and security manager (SM) protocols
■ Master and slave roles
■ API access to generic attribute profile (GATT), generic access
profile (GAP), and L2CAP
■ L2CAP connection-oriented channel
■ GAP features
❐ Broadcaster, Observer, Peripheral, and Central roles
❐ Security mode 1: Level 1, 2, and 3
❐ Security mode 2: Level 1 and 2
❐ User-defined advertising data
❐ Multiple-bond support
■ GATT features
❐ GATT client and server
❐ Supports GATT subprocedures
❐ 32-bit universally unique identifiers (UUID)
■ Security Manager (SM)
❐ LE Secure Connections (Bluetooth 4.2 feature)
❐ Pairing methods: Just Works, Passkey Entry, and Out of
Band
❐ Authenticated man-in-the-middle (MITM) protection and data
signing
■ Supports all SIG-adopted BLE profiles
Document Number: 001-95464 Rev. *H
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